Method of manufacturing a bipolar CMOS device

Details Method of manufacturing a bipolar CMOS device Method of manufacturing a bipolar CMOS device

1990-05-15

1992-03-17

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 34, 437 38, 437 33, 437 67, H01L 21328

Patent

active

050968432

ABSTRACT:
A well with a low impurity concentration is provided as a collector region on a semiconductor substrate. A trench is formed in a portion of the well from the surface toward the inside thereof. An insulating film, serving as a barrier against impurities, is formed on the side wall of the trench. Impurities are introduced through the trench and diffused to a high concentration into the well, thereby forming a high impurity concentration collector region which is connected to the collector electrode of the bipolar transistor. With the above-mentioned structure, the steps of diffusing antimony to a high concentration and growing an epitaxial silicon layer, which are indispensable to the prior art, are eliminated.

REFERENCES:
patent: 4520552 (1985-06-01), Arnould et al.
patent: 4589936 (1986-05-01), Komatsu et al.
patent: 4711017 (1987-12-01), Lammert
patent: 4835115 (1989-05-01), Eklund
patent: 4884117 (1989-11-01), Neppl et al.
patent: 4965220 (1990-10-01), Iwasaki
patent: 4975764 (1990-12-01), Hsu

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