Method of manufacturing a Bi-MOS device with a polycrystalline r

Details Method of manufacturing a Bi-MOS device with a polycrystalline r Method of manufacturing a Bi-MOS device with a polycrystalline r

1990-03-27

1991-10-22

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437162, 148DIG9, 357 43, H01L 2170

Patent

active

050595490

ABSTRACT:
A Bi-MOS semiconductor device of a type having a bipolar device and a plurality of MOS devices formed on a principal surface of a semiconductor substrate and a method of producing the same. The device includes a plurality of element isolation regions each thereof being composed of a first semiconductor region formed in the semiconductor substrate and having the same type of conductivity as the semiconductor substrate, and a thick insulation layer formed on the first semiconductor region, and at least one of an emitter electrode and a collector electrode formed in the bipolar device, gate electrodes formed in the MOS devices, a low-resistivity polycrystalline layer formed by a buried contact from one of the MOS devices and a high-resistivity portion formed by a high resistivity polycrystalline silicon layer connected to the low-resistivity polycrystalline silicon layer are formed from a polycrystalline silicon layer formed by the same layer formation.

REFERENCES:
patent: 4016596 (1977-04-01), Magdo et al.
patent: 4256515 (1987-03-01), Miles et al.
patent: 4299024 (1987-11-01), Piotrowski
patent: 4673965 (1987-06-01), Rusch
patent: 4709469 (1987-12-01), Hirao
patent: 4902640 (1990-02-01), Sachitano et al.
patent: 4912055 (1990-03-01), Min et al.
patent: 4929570 (1990-05-01), Howell

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