Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2001-01-29
2002-04-02
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
Reexamination Certificate
active
06365439
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention concerns a semiconductor integrated circuit device technique and, more in particular, it relates to a useful technique to be applied to portable equipment, such as portable telephones and handy type personal computers, for which there is a strong trend toward reducing the size, the weight and the thickness of the product.
Recently, a trend toward reducing the size, the weight and the thickness of the product has become vigorous for electronic equipment along with an improved function and performance. This is largely due to a rapid increase in the use of personal equipment, such as personal telephones or handy type personal computers in recent years. Further, man-machine interface functions have been increased in personally manipulated equipment, for which easy handlability and operability have been considered increasingly important. It is considered that the trend will become more and more conspicuous in expected regular multimedia areas.
Under such circumstances, development for increasing the density and the degree of integration of semiconductor chips has progressed continuously, however the size and the number of electrodes of the semiconductor chips have increased, while the size of the packages have also increased rapidly. Accordingly, narrowing of the pitch of terminal leads has been promoted for facilitating the size reduction of the packages, which makes mounting of the package more difficult.
In view of the above, it has been proposed in recent years to provide high density packages with super-multiple pins having the same area as that of the semiconductor chips, and such packaging techniques are mentioned, for example, in various publications, such as “Nikkei Microdevice” p 98-p 102, issued on May 1, 1994, “Nikkei Microdevice” p 96-p 97, issued on Feb. 1, 1995 by Nikkei BPCO and “Electronic Material”, p 22-p 28, issued on Apr. 1, 1995 (Heisei 7) by Kogyo Chosakai. One example of the structures produced with such packaging techniques, for example, as described in FIG. 6 of the “Electronic Material” publication, has a package structure in which a flexible wiring substrate is disposed by way of an elastomer (elastic material) on the surface of a semiconductor chip, leads on one end of wirings of the flexible wiring substrate are electrically connected with bonding pads on the surface of the semiconductor chip, and bump lands on the other end of the wirings of the flexible wiring substrate are electrically connected with the solder bumps.
The package structure has an outer size about equal to or greater than that of a semiconductor chip by the size of a protection frame optionally attached to the periphery of the chip, for which a flexible wiring substrate formed with solder bumps is used. The wiring pattern of the wiring substrate is made of a Cu foil having a Au plating on one side, the top ends of which to be connected with the pad of the chip constitute a lead pattern which is only composed of Au as a result of etching the Cu foil. In this structure, the flexible wiring substrate is bonded by an elastomer on the surface of the semiconductor chip and then the Au leads are connected with the bonding pads of the semiconductor chip.
SUMMARY OF THE INVENTION
In a study made by the present inventor of the package structure as described above, the following problems were recognized. For example, since the flexible wiring substrate in the package structure described above has a structure typically represented by a TCP (Tape Carrier Package) in which a Cu wiring pattern is formed on the surface of a polyimide tape, and an elastomer is formed to the wiring substrate on the side of the wiring surface, it is difficult to mount the elastomer uniformly and stably because of unevenness of the wiring pattern on the flexible wiring substrate. That is, there exist such problems that voids not filled with the elastomer are formed near both sides of the protrusions of the wiring pattern upon coating or appending the elastomer on the flexible wiring substrate, and the step of bonding the semiconductor chip can not be conducted stably since the size and the shape of the elastomer are not stable.
Further, bump electrodes are formed on the wiring substrate on the side of the tape. That is, a bump electrode is connected with the wirings by way of a through hole formed in the tape. Since the thickness of the tape is relatively large, for example, as much as 50 &mgr;m, if the pitch between the bump electrodes is smaller than the thickness of the tape, the aspect ratio of the through hole is increased to bring about a concern that the bump electrode and the wiring will not be connected. Accordingly, there is a concern that an increase in the number of pins of the package may be restricted.
In view of the above, an object of the present invention is to provide a semiconductor integrated circuit device capable of mounting an elastic structural material to a wiring substrate stably with a high accuracy and making the bonding step of a semiconductor chip stable, thereby enabling assembling with a high yield.
Another object of the present invention is to provide a technique for promoting an increase in the number of pins in a package.
An object of the present invention is to provide a semiconductor integrated circuit device capable of obtaining excellent electrical properties in view of noise resistance by the adoption of a multiple wiring layer structure.
An object of the present invention is to prevent wiring from becoming contaminated ingredients of an elastic structural material.
An object of the present invention is to prevent a semiconductor chip from being damaged, improve the reliability of the semiconductor chip, as well as prevent connection failure between an elastic structural material and the semiconductor chip, worsening of the flatness of the wiring substrate and lowering of reliability.
An object of the present invention is to eliminate a requirement for a soft-modified special wire bonder and to effect a shortening of the contact time upon bonding by further simplifying the trace of the bonding tool.
An object of the present invention is to solve a problem concerning disconnection of wirings.
An object of the present invention is to reduce any damage to a passivation layer or a semiconductor chip therebelow and further improve the bondability by preventing contamination of the wirings.
An object of the present invention is to increase the bonding strength between wirings and a substrate material and obtain a stable notch cutting performance.
An object of the present invention is to suppress warp of a wiring substrate and improve bondability with a bonding material, so as to constitute a package of excellent moisture proofness and reliability.
An object of the present invention is to improve the groove-fillage capability of an elastic structural material, capable of increasing the strength of a metal mask, by using a plurality of one side bridging portions, and further improving the groove-fillage capability by the formation of a stopping dam for sealant flow.
An object of the present invention is to improve the bondability and prevent damage to a semiconductor chip in an inner lead bonding technique.
An object of the present invention is to form a suitable S-shaped configuration with no return of a bonding tool but by merely driving the bonding tool vertically using a wiring design which takes into consideration a bending stress ratio.
An object of the present invention is to reduce the occurrence of cracks in wirings per se and moderate bonding damage to a semiconductor chip.
An object of the present invention is to suppress bleeding of low molecular weight ingredients of an elastic structural material and further avoid a disadvantage involving the creation of voids upon forming the elastic structural material by surface flattening.
An object of the present invention is to improve the fabrication accuracy for hole diameter for connection of a bump electrode in a method of manufacturing a semiconductor integrated circuit.
An object
Akiyama Yukiharu
Anjoh Ichiro
Hasebe Akio
Kimoto Ryosuke
Kudaishi Tomoaki
Fourson George
Hitachi , Ltd.
Pham Thanh V
LandOfFree
Method of manufacturing a ball grid array type semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a ball grid array type semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a ball grid array type semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2816691