Method of manufacture transistor having gradient doping during l

Details Method of manufacture transistor having gradient doping during l Method of manufacture transistor having gradient doping during l

1991-08-19

1993-12-28

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437128, 148DIG126, H01L 2120

Patent

active

052739295

ABSTRACT:
A power transistor comprises, on a layer of insulator, a layer of a semiconductor material comprising several zones with N+, N and N+ doping. The N doped zone corresponds to the gate zone. The N+ doped zones correspond to the drain and source zones. A method for the making of such a transistor is also disclosed. Application: the making of a field-effect transistor with improved heat dissipation.

REFERENCES:
patent: 4211586 (1980-07-01), Fang et al.
patent: 4253229 (1981-03-01), Yeh et al.
patent: 4769341 (1988-09-01), Luryi
patent: 4907053 (1990-03-01), Ohmi
patent: 4948752 (1990-08-01), Geissberger et al.
patent: 4952526 (1990-08-01), Pribat et al.
patent: 4999314 (1991-03-01), Pribat et al.
patent: 5213995 (1993-05-01), Chen et al.
Extended Abstracts of the 19th Conference on Solid State Devices and Materials, Aug. 25-27, 1987, pp. 179-182, K. Kusukawa, et al., "MOS-FETs Fabricated By SPE-SOI Technology".

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