Method of manufacture of multilayer dielectric on a III-V substr

Details Method of manufacture of multilayer dielectric on a III-V substr Method of manufacture of multilayer dielectric on a III-V substr

1994-06-06

1996-04-30

Breneman, R. Bruce

Fishing, trapping, and vermin destroying

437238, 437241, 437978, H01L 21265

Patent

active

055125182

ABSTRACT:
A manufacturable III-V semiconductor structure having small geometries is fabricated. A silicon nitride layer is formed on a III-V semiconductor material and a dielectric layer comprised of aluminum is formed on the silicon nitride layer. Another dielectric layer comprised of silicon and oxygen is formed over the dielectric layer comprised of aluminum. The dielectric layer comprised of aluminum acts as an etch stop for the etching of the dielectric layer comprised of silicon and oxygen with a high power reactive ion etch. The dielectric layer comprised of aluminum may then be etched with a wet etchant which does not substantially etch the silicon nitride layer. Damage to the surface of the semiconductor material by exposure to the high power reactive ion etch is prevented by forming the dielectric layer comprised of aluminum between the silicon nitride layer and the dielectric layer comprised of silicon and oxygen.

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R. D. J. Verhaar et al., "A 25 .mu.m 2 Bulk Full CMOS SRAM Cell Technology with Fully Overlapping Contacts", IEEE, 1990, pp. 473-476.

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