Method of manufacture for embedded processing subsystem module

Details Method of manufacture for embedded processing subsystem module Method of manufacture for embedded processing subsystem module

2000-11-14

2002-02-19

Dunn, Tom (Department: 1725)

Metal fusion bonding

Process

Plural joints

C228S246000, C029S831000, C029S840000

Reexamination Certificate

active

06347735

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to high speed and high density embedded processing systems which employ microprocessors and digital signal processors. The invention provides a Ball Grid Array module for which microprocessor companion electronics are assembled on a printed circuit board directly opposite of the microprocessor being supported, thereby reducing the board space necessary to implement the full processing circuit and reducing printed circuit board track lengths.
INCORPORATION BY REFERENCE
This application incorporates by reference the related parent application, USPTO Ser. No. 09/160,957, entitled, “Embedded Processing Subsystem Module,” filed on Sep. 25, 1998 by Robert H. Frantz, et al.
BACKGROUND OF THE INVENTION
Embedded processing systems which employ microprocessors and digital signal processors (“SP”) are well known within the art, as well as standard modular packaging schemes for subsystems. Typical subsystems including arrays or banks of memory devices, peripherals such as communications controllers, and clock circuits. Well known component packages and modules are specified by the Electronics Industries Alliance (“EIA”) JEDEC Solid State Products Division, and include package types such as Plastic Quad Flat Pack (“PQFP”), Small Outline Integrated Circuit (“SOIC”), Ball Grid Array (“BGA”), and multi-device modules such as Single Inline Memory Module (“SIMM”).
While microprocessors and DSP's have traditionally employed JEDEC standard packages, such as PQFP and BGA, the pin-to-signal assignments of a particular processor or DSP is determined by the manufacturer of the processor. Thus, two processors from different manufacturers which both utilize a particular BGA package will not necessarily have the power, ground, address, data, control, and other signals assigned to the same pins or balls on the package.
Further, as demands on board space have increased due to the need to build greater functionality into a particular form factor board, such as a VME or Peripheral Component Interconnect (“PCI”) card, new methods of packaging groups of related components are needed to conserve board space.
Finally, as processor bus speeds have increased far beyond speeds of 100 MHz, the minimization of printed circuit board (“PCB”) track lengths interconnecting microprocessor package pins to subsystem module pins in order to preserve signal integrity of high speed digital electrical signals has become increasingly important.
Therefore, there exists an need in the art for a embedded processor subsystem module which minimizes processor-to-module PCB track lengths and maximizes board space utilization. This subsystem module preferably employs standard JEDEC physical definition and requires only conventional assembly technology for PCB boards.
SUMMARY OF THE INVENTION
The object of the present invention is to provide an embedded processor subsystem module which minimizes processor-to-module PCB track lengths and maximizes board space utilization. This subsystem module employs a standard JEDEC Ball Grid Array footprint definition and requires only conventional assembly technology for PCB boards. The subsystem module ball-to-signal definitions use a “mirror image” definition of specific microprocessors or digital signal processors in order to allow the subsystem module to be mounted on the printed circuit board on the opposing PCB surface directly opposite of the processor or DSP, thereby providing a minimum track length for high speed signals and utilizing PCB board space “underneath” the processor which would ordinarily not be utilized.


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