Method of making wire connection in semiconductor device

Details Method of making wire connection in semiconductor device Method of making wire connection in semiconductor device

2000-11-07

2003-05-20

Eley, Timothy V. (Department: 3723)

Metal working

Method of mechanical manufacture

Electrical device making

C029S02700R, C029S040000, C029S041000, C029S046000

Reexamination Certificate

active

06564449

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to a method of making a wire connection in a semiconductor device, and more particularly to bonding of wire between a bonding pad on a semiconductor chip and a second bonding location.
2. Description of the Related Art
As electronic devices have become more smaller and thinner, the packages for protecting and interconnecting IC chips have the same trend, too.
Referring to
FIG. 1
, prior art wire bonding techniques make the wire interconnection between the chip bond pad
210
and the substrate contact pad
230
by making a ball bond to the chip bond pad
210
, forming a loop therebetween, and making a stitch bond to the substrate contact pad
230
to finish the wire interconnect. The normal loop height is generally about 10 to 15 mils. As thinner packages have been developed, the loop height has been reduced with conventional bonding techniques down to about 6 mils in height by changes in the loop parameters, profile and wire types. However, this loop height is considered to be a minimum obtainable loop height as attempts to go lower have caused wire damage and poor wire pull strengths.
The loop height can be reduced to about 0.002 inches by the use of an entirely different wire bonding technique disclosed in U.S. Pat. No. 5,735,030. Referring now to
FIGS. 2
a
and
2
b
, there is shown a process flow for wire bonding in accordance with U.S. Pat. No. 5,735,030. Initially, as shown in
FIG. 2
a
, a protuberance
200
is formed on the chip bond pad
210
by first ball bonding the free end of an electrically conductive wire onto the chip bond pad
210
, and thereafter stitch bonding the same wire to its ball bonded end at a point on the wire immediately adjacent the ball bonded end such that the ball bond and stitch bond together form the protuberance
200
. Thereafter, as shown in
FIG. 2
b
, using a ball bonding tool, first ball bonding one end of a bonding wire
220
to the substrate contact pad
230
and thereafter stitch bonding the other end of the bonding wire
220
to the protuberance
200
on the chip bond pad
210
. The protuberance
200
is used to prevent the ball bonding tools from damaging the passivation area of the chip immediately surrounding the pad
210
during stitch bonding of the wire
220
. However, it is very difficult to form protuberances with uniform profile by the method described in U.S. Pat. No. 5,735,030. Typically, the wires
220
are all formed by the wire bonding machine with identical operation parameters. Therefore, protuberances with irregular profile will adversely affect the stitch.bonding of wire
220
thereby reducing the reliability of finished package.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to overcome the problems and disadvantages associated with the above-described technique for making a wire connection in a semiconductor device.
In order to accomplish the object, the present invention provides a method of making a wire connection in a semiconductor device including an electrically conductive lead forming part of a substrate or leadframe, and a semiconductor chip having a bonding pad formed on the active surface thereof, the method comprising: (a) forming an under bump metallurgy (UBM) over the active surface of the chip including the bonding pad; (b) forming a gold bump on the UBM at a location corresponding to the bonding pad; (c) etching the UBM with the gold bump as a mask; and (d) connecting one end of a bonding wire to the conductive lead by ball bonding and the other end thereof to the gold bump on the bonding pad of the chip by stitch bonding. Alternatively, the semiconductor chip having bumps may be formed by electroless plating a nickel layer on the bonding pads of the chip, and followed by electroless plating a gold layer on the nickel layer. Furthermore, the method of the present invention is equally applicable where chip-to-chip connections are required.
Since the bumps of the present invention are all formed in a single step, it is easy to obtain bumps with good uniformity, i.e., having a uniform profile. This will significantly enhance the reliability of reverse wire bonding thereby obtaining a low profile package without sacrificing the reliability thereof.


REFERENCES:
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patent: 5476211 (1995-12-01), Khandros
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patent: 6162664 (2000-12-01), Kim
patent: 6291271 (2001-09-01), Lee et al.
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