Method of making wafer level chip scale package

Details Method of making wafer level chip scale package Method of making wafer level chip scale package

2001-02-20

2002-07-16

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

Subsequent separation into plural bodies

C438S113000

Reexamination Certificate

active

06420244

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor package, and more particularly to a wafer level chip scale package (WLCSP) and a method for fabricating the same.
2. Description of Prior Art
As electronic devices have become more smaller and thinner, the velocity and the complexity of IC chip become more and more higher. Accordingly, a need has arisen for higher packaging efficiency. Demand for miniaturization is the primary catalyst driving the usage of advanced packages such as chip scale packages (hereinafter referred as CSP) and flip chips. Both of them greatly reduce the amount of board real estate required when compared to the alternative ball grid array (hereinafter referred as BGA) and thin small outline package (hereinafter referred as TSOP). Typically, a CSP is 20 percent larger than the chip itself. The most obvious advantage of the CSP is the size of the package; that is, the package is slightly larger than the chip. Another advantage of the CSP is that the package facilitates test and burn-in before assembly as an alternative to known good die (KGD) testing. In addition, the CSP can combine many of the benefits of surface mount technology (SMT), such as standardization, encapsulation, surface mount, and reworkability, with the benefits of flip chip technology, such as low inductance, high I/O count, and direct thermal path.
However, as compared with conventional BGA or TSOP, the CSP has the disadvantage of higher manufacturing cost. However, this problem could be eliminated if the CSPs could be mass produced more easily. Therefore, the semiconductor packaging industry has tried to develop mass production techniques at the wafer-level for manufacturing the chip-sized packages, as illustrated in U.S. Pat. Nos. 5,323,051, 5,925,936 and 6,004,867.
According to the wafer level chip scale packages disclosed in the above-mentioned U.S. Patents, each chip of the wafer is encapsulated before die sawing. After the wafer is encapsulated, each encapsulated wafer is sawed to form an individual semiconductor package unit. However, the sides of the semiconductor package unit are exposed to the ambient environment, and thus the semiconductor package is liable to be damaged by the moisture, and the reliability and service life of such semiconductor package unit will be greatly affected. Therefore, semiconductor package manufacturers try to develop a new fabrication method of wafer level chip scale package to provide a better isolation for moisture.
SUMMARY OF THE INVENTION
A primary object of the invention is to provide a method for fabricating the wafer level chip scale package in mass-production, thereby significantly decreasing manufacturing cost thereof.
Another object of the invention is to provide a method for fabricating the wafer level chip scale package, wherein the chip scale package has a structure with better moisture isolation so as to prevent the chips from damage by moisture.
In order to achieve the above-mentioned objects, the method for making the wafer level chip scale package according to the present invention mainly comprises the steps of: disposing a wafer on the top surface of a retractable film, the wafer having a plurality of chips and a plurality of cutting lines therebetween, each chip having a plurality of bonding pads; cutting the wafer into individual chips along the cutting lines; stretching the retractable film so as to separate the cut chips from one another with a predetermined distance; molding the cut wafer in order to encapsulate the bonding pads and sides of each chip completely; grinding the encapsulated chip to expose the bonding pads out of the molding compound; and sawing the encapsulated chips into individual semiconductor package unit.
According to the method for fabricating the wafer level chip scale package, the retractable film is secured by a frame, which is fixed by a fixture. The retractable film is displaced on a work platform and this platform can move up, with respect to the fixture, to stretch the retractable film such that each chip is separated from one another with a predetermined distance. The encapsulated wafer is sawed into individual semiconductor package unit by a cutter, wherein the predetermined distance between each chip is larger than the thickness of the cutter. Hence, the sides of individual semiconductor package unit are encapsulated by the molding compound. Therefore, the method of fabricating the wafer level chip scale package according to the present invention can provide a better result of moisture isolation and prevent the semiconductor chip from destroying by moisture.


REFERENCES:
patent: 5323051 (1994-06-01), Adams et al.
patent: 5430325 (1995-07-01), Sawada et al.
patent: 5654582 (1997-08-01), Kijima et al.
patent: 5925934 (1999-07-01), Lim
patent: 5925936 (1999-07-01), Yamaji
patent: 5950070 (1999-09-01), Razon et al.
patent: 5994783 (1999-11-01), You
patent: 6004867 (1999-12-01), Kim et al.
patent: 6046504 (2000-04-01), Kimura
patent: 57017152 (1982-01-01), None

Affiliated with

Also associated with

Rating

Method of making wafer level chip scale package does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making wafer level chip scale package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making wafer level chip scale package will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2918793