Method of making virtual ground memory cell array

Fishing – trapping – and vermin destroying

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437 43, 437 44, 437 48, 437229, H01L 2170

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053066588

ABSTRACT:
A memory cell array for a nonvolatile memory device having single-transistor cells (10). Row lines (15) connect the control gates of each row of cells. Column lines (17) connect the drain regions (11) and source regions (12) of columns of cells, such that pairs of row-adjacent cells share a column line (17). Each shared column line (17) has two junctions for each pair of cells that share the column line. One junction is graded for source regions (12) and the other is abrupt for drain regions (11).

REFERENCES:
patent: 4804637 (1989-02-01), Smayling et al.
patent: 4851361 (1989-07-01), Schuman et al.
patent: 5019879 (1991-05-01), Chiu

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