Method of making vertical PNP transistor

Details Method of making vertical PNP transistor Method of making vertical PNP transistor

1992-03-17

1993-03-02

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 26, 148DIG10, 148DIG11, H01L 21265, H01L 2970

Patent

active

051908840

ABSTRACT:
A vertical PNP transistor for use in an integrated circuit is disclosed. A P-type substrate serves as collector. An N-type epitaxial layer is formed on the substrate and serves as base. A P-type region is formed in the epitaxial layer and serves as emitter. An N.sup.+ -type localized buried layer is formed on the substrate in the area beneath the emitter. The localized buried layer covers less than all of the area under the emitter. An N.sup.+ -type sinker region is formed through the epitaxial layer, connecting to the localized buried layer and serving as a connection to the base of the vertical PNP transistor.

REFERENCES:
patent: 3925120 (1975-12-01), Saida et al.
patent: 4151540 (1979-04-01), Sander et al.
patent: 4404738 (1983-09-01), Sasaki et al.
patent: 4826780 (1989-05-01), Takemoto et al.
patent: 4949150 (1990-08-01), Giannella
patent: 4985741 (1991-01-01), Bauer et al.
patent: 5097309 (1992-03-01), Giannella

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