Method of making vertical MOSFET with sub-trench source contact

Fishing – trapping – and vermin destroying

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

257328, 148DIG126, H01L 21265

Patent

active

056935471

ABSTRACT:
An integrated circuit transistor vertically oriented along a side wall of a shallow trench formed in a semiconductor substrate. The transistor includes a semiconductor substrate, preferably comprised of silicon, into which a shallow transistor trench has been formed. A trench floor of the transistor trench is vertically displaced below the upper surface of the semiconductor substrate by a trench depth. The transistor further includes a drain impurity distribution having a peak concentration that is vertically displaced a drain depth below the semiconductor substrate upper surface. The drain depth is less than the trench depth. The transistor further includes a channel impurity distribution having a peak concentration vertically displaced a channel depth below the substrate upper surface. The channel depth is greater than the drain depth, but less than the trench depth. The drain impurity distribution and the channel impurity distribution extend laterally to a first side wall of the transistor trench. The transistor further includes a source impurity distribution having a peak concentration vertically displaced a source depth below the substrate upper surface. The source depth is greater than the channel depth. The source impurity distribution further includes a source lower boundary vertically displaced a source boundary depth below the upper surface of the semiconductor substrate. The source impurity distribution extends laterally to a contact region of the semiconductor substrate below the trench floor. The transistor further includes a gate dielectric in contact with the first trench side wall and a conductive gate formed in contact with the gate dielectric.

REFERENCES:
patent: 5010386 (1991-04-01), Groover, III
patent: 5032529 (1991-07-01), Beitman et al.
patent: 5164325 (1992-11-01), Cogan et al.
patent: 5326711 (1994-07-01), Malhi
patent: 5424231 (1995-06-01), Yang
patent: 5474943 (1995-12-01), Hshieh et al.
patent: 5567634 (1996-10-01), Herbert et al.
patent: 5578508 (1996-11-01), Baba et al.
patent: 5583060 (1996-12-01), Hertrich et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of making vertical MOSFET with sub-trench source contact does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making vertical MOSFET with sub-trench source contact, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making vertical MOSFET with sub-trench source contact will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-800760

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.