Method of making tri-well CMOS by self-aligned process

Details Method of making tri-well CMOS by self-aligned process Method of making tri-well CMOS by self-aligned process

1985-09-20

1987-10-06

Roy, Upendra

Fishing, trapping, and vermin destroying

148DIG82, 357 42, 357 91, 437 41, 437 57, H01L 2122, H01L 754, H01L 21263

Patent

active

046973320

ABSTRACT:
A semiconductor structure having at least three types of wells which may be of different doping levels and methods of manufacturing such a structure, are disclosed. In one method, regions which will become active devices are protected with a nitride layer as the associated well-regions are implanted. In another method, previously implanted wells are covered with thick oxide which in combination with the nitride layer provides automatic alignment of adjacent wells. In yet another method, implanted wells are covered with oxide while a last well is implanted with this last well being defined by both thick oxide and photoresist. All methods avoid a masking step and avoid the need for aligning the edge of a later photoresist mask with the edge of an earlier photoresist mask. The structures formed by these methods may have heavily-doped P wells, heavily-doped N wells, and lightly-doped P or N wells, or both, for forming higher breakdown voltage devices on the same chip with lower breakdown voltage devices.

REFERENCES:
patent: 4554726 (1985-11-01), Hillenius et al.
patent: 4584027 (1986-04-01), Metz et al.
patent: 4601098 (1986-07-01), Oda
IBM Tech. Disc. Bull., 27 (Apr. 1985), 6806.
IBM, TDB, 27 (Apr. 1985), 6717.

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