Method of making trench isolation structures with oxidized...

Details Method of making trench isolation structures with oxidized... Method of making trench isolation structures with oxidized...

1997-11-12

2001-02-06

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S432000

Reexamination Certificate

active

06184108

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to trench isolation structures in semiconductors and, more particularly, to trench isolation structures having oxide materials deposited within a trench.
2. Description of the Related Art
Trench isolation structures are used to isolate transistors and logic gates in high density semiconductor devices such as microprocessors, non-volatile memories, and programmable logic arrays.
FIGS. 1A-1C
are diagrams summarizing the formation of a conventional trench isolation structure
10
by etching a trench opening
12
into the semiconductor substrate
5
having on the substrate surface an oxide layer
7
and a silicon nitride layer
9
. As shown in
FIG. 1A
, the trench opening
12
has sidewalls
12
a
and
12
b
and a width of approximately 0.5 micron. The conventional process then uses low pressure chemical vapor deposition (LPCVD) to deposit an oxide such as tetraethylorthosilicate (TEOS) to fill the trenches, typically by depositing a layer of oxide having a thickness of greater than half the trench width on each wall of the trench. Specifically, if the trench
12
has a width of 0.5 micron and the oxide layer
14
had a thickness of less than 0.25 micron, the deposited oxide layer
14
a
would form a structure having a gap
15
as shown in FIG.
1
B. To avoid formation of the gap, the deposited oxide layer
14
typically has a thickness of greater than one half the trench width to form the structure in FIG.
1
C.
As shown in
FIG. 1C
, however, a seam
16
tends to form in the trench isolation structure at the boundary where the two oxide portions
14
a
and
14
b
of the oxide layer
14
meet. Although the actual location of the seam
16
may vary depending on the relative thicknesses of the deposited oxide layer
14
a
and
14
b
, the seam
16
will form where the layers
14
a
and
14
b
meet.
Formation of the seam creates problems that will reduce the yield of the semiconductor device. For example, the seam
16
may open during manufacture, such as during planarization that involves etch-back or chemical-mechanical-polishing (CMP) processing of the oxide layer
14
. Etch-back of the deposited oxide layer
14
causes the upper end of the seam
16
to open at a faster rate, resulting in a “V” formation that can collect materials deposited during fabrication. Accelerated etching of the seam
16
may also create electrically conductive stringers formed from subsequently deposited materials such as polysilicon, metal or silicide. These stringers cannot be removed because the deposited material is embedded in the “V” formation. Thus, the stringers can cause shorts between poly and metal lines and therefore reduce the product yield.
DISCLOSURE OF THE INVENTION
There is a need for a trench isolation structure that provides a seamless oxide layer filling the trench opening of a trench isolation structure.
There is also a need for a trench isolation structure that improves product yield by freedom from those defects typically carried by etched seams and deposited oxide layers.
There is also a need for a trench isolation structure having no seam defects between oxide layers within the trench opening.
These and other needs are achieved by the present invention, wherein a trench isolation structure in a semiconductor substrate includes a trench opening and a seamless oxide region filling the trench. The trench isolation structure includes a first oxide layer overlying the bottom and sidewalls of the trench and forming a gap within the trench. A second oxide layer filling the gap is formed from oxidation from silicon deposited within the gap. The surface of the trench isolation structure which results is free from seams, and thus prevents the introduction of impurities such as polysilicon or silicide during subsequent fabrication of semiconductor circuits.
According to the present invention, a method of forming a trench isolation structure in a semiconductor substrate comprises the steps of: forming a silicon nitride mask overlying the semiconductor substrate such that the silicon nitride mask has an exposed portion corresponding to the location of a trench to be etched; etching a trench opening in the semiconductor substrate at the exposed portion; forming a first oxide layer that covers the bottom and side surfaces of the trench opening and with a gap exposed within the trench opening; adding silicon material to the gap; and heating the silicon material to form a second oxide layer, the second oxide layer upon formation expanding to fill the gap.
The first oxide layer overlying the bottom and sidewalls of the trench provides stress relief for the sidewalls during formation of the second oxide layer. Thus, the present invention provides a trench isolation structure with an oxide region having a seamless surface filling the trench, thereby preventing the formation of stringers.
The present invention also provides the use of spacers formed within exposed portions of the nitride mask before etching of the trench. Hence, the trench has a width that is narrower than the width of the exposed portions of the nitride mask. Thus, the use of spacers is particularly effective in overcoming limitations of conventional masking techniques, such as photolithography.


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patent: 4493740 (1985-01-01), Komeda
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