Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Reexamination Certificate
2007-03-27
2010-06-29
Lee, Hsien-ming (Department: 2823)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
With electrical circuit layout
C257SE21598
Reexamination Certificate
active
07745265
ABSTRACT:
A method of making a monolithic, three dimensional NAND string, includes forming a select transistor, forming a first memory cell over a second memory cell, forming a first word line for the first memory cell, forming a second word line for the second memory cell, forming a bit line, forming a source line, and forming a select gate line for the select transistor. The first and the second word lines are not parallel to the bit line, and the first and the second word lines extend parallel to at least one of the source line and the select gate line.
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Mokhlesi Nima
Scheuerlein Roy
Foley & Lardner LLP
Lee Hsien-ming
Parendo Kevin
Sandisk 3D LLC
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