Method of making three dimensional integrated circuit interconne

Details Method of making three dimensional integrated circuit interconne Method of making three dimensional integrated circuit interconne

1993-09-02

1995-01-24

Arbes, Carl J.

Metal working

Method of mechanical manufacture

Electrical device making

29856, 437205, 437209, H05K 336

Patent

active

053832698

ABSTRACT:
A three dimensional integrated circuit interconnect for connecting a plurality of chips in a module with a standard footprint for pin grid array or quad flat pack mounting. Each IC is mounted on a custom interconnect slice and tested. The slices are stacked together with electrical connections from one slice layer to the next. The module may use multi-layer ceramic slices or printed circuit board materials.

REFERENCES:
patent: 2907924 (1959-10-01), Lutton
patent: 3345344 (1967-10-01), Fetscher et al.
patent: 3705332 (1972-12-01), Parks
patent: 3746934 (1973-07-01), Stein
patent: 4103318 (1978-07-01), Schwede
patent: 4355463 (1982-10-01), Burns
patent: 4466183 (1984-08-01), Burns
patent: 4480067 (1984-10-01), Vio et al.
patent: 4525921 (1985-07-01), Carson et al.
patent: 4532046 (1985-07-01), Meunier et al.
patent: 4536296 (1985-08-01), Vio
patent: 4560826 (1985-12-01), Burns et al.
patent: 4587300 (1986-05-01), Vio et al.
patent: 4630172 (1986-12-01), Stenerson et al.
patent: 4767540 (1988-08-01), Spitzer et al.
patent: 4862249 (1989-08-01), Carlson
patent: 4862588 (1989-09-01), MacKay
patent: 4868712 (1989-09-01), Woodman
patent: 4884237 (1989-11-01), Mueller et al.
patent: 4902751 (1990-02-01), Lewellyn et al.
patent: 4953060 (1990-08-01), Lauffer et al.
patent: 4991290 (1991-02-01), McKay
patent: 5013249 (1991-05-01), Lindeman et al.
patent: 5016138 (1991-05-01), Woodman
patent: 5028986 (1991-07-01), Sugano et al.
patent: 5036431 (1991-07-01), Adachi et al.
patent: 5065277 (1991-11-01), Davidson
patent: 5099928 (1992-03-01), Bouchut et al.
patent: 5128420 (1992-07-01), Domb et al.
patent: 5279029 (1994-01-01), Burns
Emory Garth, "Memory System-An Ultimate In Packaging Technology", Electro 78 Conference, Boston, Mass., pages unknown, 23 May 1978.
Shankar et al. in Bull, Mater. Sci.; vol. 10; pp. 423-433 (1988).
Clauss et al. in Int. J. Miner. Proc.; vol. 3; p. 27 (1976).
Schmieg, "DIP Storage Module With Stacked Chips," IBM Technical Disclosure Bulletin, vol. 23, No. 6, p. 2337, Nov. 1980.
"3-D Memory Module," Irvine Sensors Corporation, Sep., 1989.
"Short Form Catalog-1991," Dense Pac Microsystems, Inc., 1991.
"Stacked Chips=More Memory," Design News, Mar. 25, 1991, p. 186.
Brochure, Conductive Circuit Corp.
Balde, "Multichip Modules: The Constructions in Use Today," Proceedings of the Technical Program of the National Electronic Packaging and Production Conferrence, NEPCON West '90 pp. 965-974.
Torku et al., "Quality Level and Fault Coverage For Multichip Modules," IEEE 20th Design Automation Conference, Paper 15.2, 1983, pp. 201-206.
Hagge, "Mechanical Considerations For Reliability Interfaces In Next Generation Electronics Packaging," Proceedings of the IEEE 1989 National Aerospace and Electronics Conference, 1989, pp. 201-206.
D. Stys et al., "A Study of Electrical Performance for Next Generation Instic Packages," IEEE-CHMT 41st Conference, May, 1991, pp. 278-282.
Quint et al., "Measurements of R, L, and C Parameters in VLSI Packages" Hewlett-Packard Journal, Oct., 1990, p. 73.
Choksi et al., "Computer Aided Electrical Modeling of VLSI Package" Electronic Components and Technology Conference, 1990, pp. 169-170.
Adams, "Chasing the Elusive Gigaflop In a Soup Can," Military and Aerospace Electronics, Feb. 1991, pp. 26-29.
Goldmann, "Universal Electronic Package", IBM Technical Disclosure Bulletin, vol. 27, No. 6, Nov. 1984, pp. 3335-3336.

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