Method of making thin film transistor with offset drain

Details Method of making thin film transistor with offset drain Method of making thin film transistor with offset drain

1995-12-06

1997-09-23

Niebling, John

Fishing, trapping, and vermin destroying

437 21, 437 41, 437 44, 437 45, H01L 2184, H01L 21265

Patent

active

056703996

ABSTRACT:
A method of forming a thin film transistor of a first conductivity type includes, a) providing a thin film transistor layer of semiconductive material; b) first masking the thin film transistor layer to mask a desired drain offset region while leaving a desired channel region exposed; c) with the first masking in place, doping the exposed channel region with a conductivity enhancing impurity of a second type; d) second masking the thin film transistor layer to mask the channel region and the drain offset region and leave desired opposing source/drain regions exposed; and e) with the second masking in place, doping the exposed source/drain regions with a conductivity enhancing impurity of the first type. A thin film transistor includes, ii) a thin film layer of semiconductive material, the thin film layer comprising a source region, a drain region, a drain offset region and a channel region; the source and drain regions being conductively doped with a conductivity enhancing impurity of the first type to a concentration effective to render such source and drain regions electrically conductive; the channel region being doped with a conductivity enhancing impurity of a second type to a first concentration; the drain offset region being doped with a conductivity enhancing impurity of the second type to a second concentration, the second concentration being less than the first concentration; and ii) a gate positioned operatively adjacent the channel region. Alternately, the drain offset region consists essentially of undoped semiconductive material.

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Wolf, "Silicon Processing for the VLSI Era vol. 2; Process Integration", pp. 66-69, Lattice Press 1990 Month unknown.
Furuta, Hiroshi et al., "Hot-Carrier Induced Ion/Ioff Improvement Of Offset PMOS TFT", NEC Corporation, 1991, pp. 27-28, month unknown.
Ohkubo, H. et al., "16 Mbit SRAM Cell Technologies for 2.0V Operation", IEDM, 1991, pp. 481-484, month unknown.

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