Method of making thin film transistor with channel and drain adj

Details Method of making thin film transistor with channel and drain adj Method of making thin film transistor with channel and drain adj

1994-08-29

1995-07-11

Thomas, Tom

Fishing, trapping, and vermin destroying

437 40, 437 44, 437915, H01L 21336

Patent

active

054321026

ABSTRACT:
A thin film transistor and a method which forms a channel region (c), a lightly doped drain region (LDD) region and, optionally, an offset region (o), in a portion of a semiconductor layer which is adjacent a sidewall of the gate electrode without the use of photo masks, thereby increasing the permissible degree of miniaturization and improving production yield.

REFERENCES:
patent: 4581623 (1986-04-01), Wang
patent: 4651408 (1987-03-01), MacElwee
patent: 4987092 (1991-02-01), Kobayashi et al.
patent: 4997785 (1991-03-01), Pfiester
patent: 5122476 (1992-06-01), Fazan et al.
patent: 5286664 (1994-02-01), Horiuchi et al.
"High Reliability & High Performance ,35.mu.M Gate-Inverted TFT'S for 16M Bit SRAM Application Using Self-Aligned LDD Structures" C. T. Liu et al., IEDM Digest, Dec. 1992, pp. 823-826.

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