Method of making stacked E-cell capacitor DRAM cell

Details Method of making stacked E-cell capacitor DRAM cell Method of making stacked E-cell capacitor DRAM cell

1991-03-19

1991-10-01

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437233, 437919, 357 236, H01L 2170

Patent

active

050533517

ABSTRACT:
An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to hereinafter as a stacked E cell or SEC. The SEC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The SEC is made up of a polysilicon storage node structure having an E-shaped cross-sectional upper portion and a lower portion making contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed SEC capacitor. With the 3-dimensional shape and a texturized surface of a polysilicon storage node plate, substantial capacitor plate surface area of 3 to 5X is gained at the storage node.

REFERENCES:
patent: 4742018 (1988-05-01), Kimura et al.
patent: 4953126 (1990-08-01), Ema
patent: 5021357 (1991-06-01), Taguchi et al.
"A Spread Stacked Capacitor (SCC) Cell for 64MBit DRAMS", by S. Knoue et al., pp. 31-34.
"3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS", by T. Ema et al., pp. 592-595.

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