Method of making stacked die assemblies and modules

Details Method of making stacked die assemblies and modules Method of making stacked die assemblies and modules

2000-03-30

2002-01-08

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S109000, C438S110000

Reexamination Certificate

active

06337225

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to a method for making semiconductor devices. More specifically, the present invention relates to a method for making stacked die assemblies and/or modules comprising at least one stacked die assembly including a plurality of vertically arranged semiconductor integrated circuit dies mounted on a suitable substrate surface.
BACKGROUND OF THE INVENTION
Integrated circuit (IC) semiconductor devices are typically formed from silicon (Si) or gallium arsenide (GaAs) wafers such that a plurality of individual devices are simultaneously formed on or within the same wafer. The finished wafers are then segmented, as by sawing, to form a plurality of discrete square or rectangularly-shaped IC units, termed a “die” or “chip”. The continued increase in the density of IC-based devices, i.e., the number of transistors, etc., per cm
2
of die or chip area, has necessitated formation of multi-chip devices in a single package, i.e., wherein a plurality of dies or chips are vertically stacked. In many instances, such vertically stacked multi-chip modules can be fabricated faster and at less cost than by developing new substrate technology.
Multi-chip module technology is advantageous in view of the significant increase in device density per substrate unit area provided thereby. In turn, the increased device density yields corresponding improvements in signal propagation speed and overall device weight not obtainable by other means. Current multi-chip module fabrication technology typically utilizes a printed circuit board substrate to which a vertically stacked series of IC components or devices are directly adhered and electrically connected, as by wire bonding, tape automated bonding (TAB), flip-TAB, flip-chip, etc., techniques.
According to conventional methodology for fabricating vertically stacked die type multi-chip modules such as disclosed in, for example, U.S. Pat. Nos. 5,291,061 and 5,323,060, the entire disclosures of which are incorporated herein by reference, a first IC die or chip is attached to the circuit board substrate, as by adhesive bonding, and wire bonded to the substrate, followed by adhesive bonding thereon of at least a second IC die or chip, thereby forming a vertically stacked assembly of dies or chips. However, this conventional procedure entails a significant problem or difficulty associated with the attachment (i.e., bonding) of the first (i.e., lowermost) die or chip to the substrate surface, arising from a combination of substrate non-planarity and thinness, thus brittleness or fragility, of the semiconductor wafers utilized in manufacture of the IC dies or chips, i.e., 6-6.5 mils. thick wafers. In particular, substrate non-planarity and the extreme thinness of currently employed IC dies or chips can lead to warping of the first (i.e., lowermost) die of the stack, which deviation from non-planarity can be replicated by each of the overlying IC dies or chips of the vertical stack. In extreme instances, the stresses arising from the lack of planarity can cause breakage, as by fracture, of one or more dies or chips of the stack, resulting in reduction in product yield and/or device failure.
Accordingly, there exists a need for improved methodology for reliable manufacture of multi-chip assemblies and modules which avoids the drawbacks attendant upon fabrication according to conventional manufacturing processes, which methodology does not incur damage to the fragile, brittle semiconductor IC dies or chips, and which is fully compatible with the throughput requirements of mass manufacturing techniques.
The present invention, wherein first and second IC dies or chips are adhesively bonded together to form a more robust (i.e., rigid) stacked structure prior to adhesively bonding the lowermost die or chip to the substrate surface, effectively addresses and solves the above-described problems associated with bonding of a single, very thin and fragile IC die or chip to the substrate. Further, the methodology provided by the present invention enjoys diverse utility in the manufacture of variously configured multi-chip device arrangements and constructions.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is an improved method of making a stacked die assembly mounted on a substrate surface.
Another advantage of the present invention is an improved method of forming a stacked die module comprising a plurality of stacked die assemblies mounted on a substrate surface.
Yet another advantage of the present invention is an improved stacked die assembly mounted on a substrate surface.
Still another advantage of the present invention is an improved stacked die module comprising a plurality of stacked die assemblies formed on a substrate surface.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to one aspect of the present invention, the foregoing and other advantages are obtained in part by a method of making a stacked die assembly mounted on a substrate surface, which method comprises the steps of:
(a) providing a substrate having a surface for mounting thereon at least one stacked die assembly;
(b) providing first and second semiconductor wafers, each of said wafers including a plurality of semiconductor integrated circuit (IC) devices in the form of dies or chips each having a pair of opposed major surfaces;
(c) segmenting the first semiconductor wafer to form a plurality of discrete first dies or chips;
(d) bonding one of the pair of opposed major surfaces of each of the discrete first dies or chips to one of the pair of opposed major surfaces of a respective die or chip of the second semiconductor wafer;
(e) segmenting the second wafer to form a plurality of stacked die assemblies each comprising a stacked, bonded pair of discrete first and second dies or chips; and
(f) bonding the other one of the pair of opposed major surfaces of the discrete second die or chip of one of the stacked die assemblies to the substrate surface.
According to embodiments of the present invention, a method for making a stacked die module comprising a plurality of stacked die assemblies mounted on a substrate surface comprises a further step (g) of repeating step (f) at least once to bond at least one additional stacked die assembly formed in step (e) to the substrate surface.
According to further embodiments of the present invention, the method of making a stacked die assembly mounted on a substrate surface comprises the further steps of:
(g) providing an additional semiconductor wafer including a plurality of semiconductor IC devices in the form of dies or chips each having a pair of opposed major surfaces;
(h) segmenting the additional semiconductor wafer to form a plurality of discrete additional dies or chips; and
(i) bonding one of the pair of opposed major surfaces of one of the plurality of discrete additional dies or chips to the other one of the pair of opposed major surfaces of the first discrete die or chip of the stacked die assembly bonded to the substrate surface, wherein steps (g)-(i) can be repeated n times, as desired, with n being an integer equal to or greater than 1.
According to particular embodiments of the present invention: step (a) comprises providing a circuit board substrate, e.g., a printed circuit board (PCB) substrate including contacts and/or conductors for making electrical connection to at least one of the first and second discrete dies or chips of the stacked die assembly; step (b) comprises providing first and second semiconductor wafers comprising first and second IC devices which are the same or different, and are comprised of silicon (Si) or gallium arsenide (GaAs); steps (c) and (e) each comprise utilizing a diamond saw

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