Method of making stackable semiconductor chips to build a stacke

Details Method of making stackable semiconductor chips to build a stacke Method of making stackable semiconductor chips to build a stacke

1998-11-02

2000-09-26

Bowers, Charles

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

438109, 438110, 438113, H01L 2148, H01L 2150

Patent

active

061241490

ABSTRACT:
A stackable semiconductor chip package, methods of fabricating the chip package, and a stacked semiconductor chip module are disclosed. In the chip package or the chip module, lateral surfaces of each semiconductor chip are insulated with insulation regions that are formed while the chip is still part of an uncut wafer. The fabrication methods include the steps of: preparing an uncut wafer having multiple chip portions; forming slots along a pair of opposed lateral sides of the chip portions; filling the slots with an insulating material; forming a first insulation layer on an upper surface of the wafer; forming via holes in the first insulation layer so that chip pads formed in each chip portion are exposed through the via holes; forming a plurality of conductive patterns on the first insulation layer so that the conductive patterns are electrically coupled to the chip pads through the via holes; forming a second insulation layer on the conductive patterns and the first insulation layer; and cutting the wafer along the cutting lines. In alternate methods, two or more wafers may be stacked before the cutting step is performed. This results in the formation of multiple stacked chip modules.

REFERENCES:
patent: 5675180 (1997-10-01), Pedersen et al.
patent: 5904502 (1999-05-01), Ference
patent: 5952725 (1999-09-01), Ball

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