Metal working – Method of mechanical manufacture – Assembling or joining
Patent
1985-09-19
1987-05-05
Chaudhuri, Olik
Metal working
Method of mechanical manufacture
Assembling or joining
29578, 156646, 156647, 156651, 148DIG115, H01L 2136, H01L 21308
Patent
active
046620591
ABSTRACT:
A MOS/SOI field-effect transistor is made by applying a layer of a photoresist over the surface of a single-crystalline silicon layer which is on a substrate of an insulating material, such as sapphire. The surface of the silicon layer is along a (100) crystallographic plane. The photoresist layer is defined to provide an area of the photoresist layer over the area of the silicon layer where the transistor is to be formed with the edges of the photoresist area being along the edges of (100) crystallographic planes which are perpendicular to the surface of the silicon layer. The portion of the silicon layer around the photoresist layer is etched with an anisotropic plasma etch which etches the silicon layer along the (100) crystallographic planes which are perpendicular to the surface of the silicon layer to form an island of the silicon. The etching is achieved by a two step process in which the first step etches part way through the silicon layer and the second step etches completely through with an overetch. This forms the silicon island with sides which extend along (100) crystallographic planes substantially perpendicular to the top surface and which are smooth, undamaged and have rounded edges with the top surface. After removing the photoresist, a MOS field-effect transistor is formed on the island.
REFERENCES:
patent: 3890632 (1975-06-01), Ham et al.
patent: 4241359 (1980-12-01), Izumi et al.
patent: 4255230 (1981-03-01), Zajac
patent: 4278987 (1981-07-01), Imaizumi et al.
patent: 4426246 (1984-01-01), Kravitz et al.
patent: 4496418 (1985-01-01), Ham
"MOS C-t Evaluation of Reactive Ion Etched Silicon Substrate" by Y. Ozaki et al., Japanese Journal of Applied Physics, vol. 23, Nov. 1984, pp. 1526-1531.
"Study of Breakdown Fields of Oxides Grown on Reactive Ion Etched Silicon Surface: Improvement of Breakdown Limits by Oxidation of the Surface", N. Lifshitz, Journal Electrochemical Society: Solid-State Science and Technology, Jul. 1983, pp. 1549-1550.
"Radiation-Hard 16K CMOS/SOS Clocked Static Ram" by A. Gupta et al. IEDM 81, pp. 616-619 (1981).
"Plasma Deposition and Etching Reactors for Semiconductor Applications" by J. Vossen, Pure and Applied Chemistry, vol. 52, (1980), pp. 1759-1765.
"Reactive Ion Etching of Silicon with Cl.sub.2 /AR(1)" by H. B. Pogge et al., Journal Electrochemical Society: Solid-State Science and Technology, Jul. 1983, pp. 1592-1597.
Morris Wesley H.
Smeltzer Ronald K.
Chaudhuri Olik
Cohen Donald S.
Morris Birgit E.
Plantz Bernard F.
RCA Corporation
LandOfFree
Method of making stabilized silicon-on-insulator field-effect tr does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of making stabilized silicon-on-insulator field-effect tr, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making stabilized silicon-on-insulator field-effect tr will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2392255