Method of making single polysilicon self-aligned bipolar transis

Details Method of making single polysilicon self-aligned bipolar transis Method of making single polysilicon self-aligned bipolar transis

1994-11-17

1996-05-14

Fourson, George

Fishing, trapping, and vermin destroying

437101, 437193, 437909, 437940, 148DIG10, 257565, 257588, 257592, H01L 21265

Patent

active

055167080

ABSTRACT:
A self-aligned single polysilicon bipolar transistor structure and a method of formation thereof are provided. The transistor has an emitter structure characterised by T shape defined by inwardly extending sidewall spacers formed by oxidation of amorphous or polycrystalline silicon, rather than the conventional oxide deposition and anisotropic etch back. Advantageously the method compatible with bipolar CMOS processing and provides a single polysilicon self-aligned bipolar transistor with a reduced number of processing steps. Further the formation of inwardly extending sidewalls defining the emitter width reduces the emitter base junction width significantly from the minimum dimension which is defined by photolithography, while a large area emitter contact is also provided.

REFERENCES:
patent: 4784966 (1988-11-01), Chen
patent: 4789885 (1988-12-01), Brighton et al.
"50-GHz Self-Aligned Silicon Bipolar Transistors with Ion-Implanted Base Profiles" James Warnock et al IEEE Electron Device Letters, vol., 11, No. 10, Oct. 1990 pp. 475-477.
"A High-Speed Bipolar Technology Featuring Self-Aligned Single-Poly Base and Submicrometer Emitter Contacts" W. M. Huang, et al IEEE Electron Device Letters, vol., 11, No. 9, Sep. 1990 pp. 412-414.
"Electron Recombination at the Silicided Base Contact of an Advanced Self-Aligned Poly-Silicon Emitter" J. L. de Jong, et al IEEE 1988 Bipolar Circuits & Technology Meeting Paper 9.5, pp. 202-205, 1988.
"An Advanced Bipolar Transistor with Self-Aligned Ion-Implanted Base and W/Poly Emitter" Tze-Chiang Chen, et al IEEE Transactions on Electron Devices, vol., 35, No. 8, Aug. 1988, pp. 1322-1327.
"Silicon Processing for the VLSI Era vol. 2, Process Interpretation" (1990) S. Wolf pp. 516-520.

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