Method of making single layer personalization

Details Method of making single layer personalization Method of making single layer personalization

1991-11-15

1993-04-27

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437206, 148DIG20, H01L 2160

Patent

active

052061841

ABSTRACT:
A process for implementing logic units using base cells and implementing an electrical connection between the logic units in a gate array. The process includes determining a connection path between the base cells and connecting the base cells at the second metalization layer using a portion of the first metalization layer. This is possible due to the gate array having vertical first metalization layer segments of the first metalization layer positioned vertically in the channel between the rows of base cells, wherein each of the vertical segments has vias in the insulation layer between the first metalization layer and the second metalization layer at its endpoints for connecting the metalization layers. Similarly, the individual transistors which comprise the base cell are coupled using the second metalization layer to implement a specific logic unit.

REFERENCES:
patent: 4682201 (1987-07-01), Lipp
patent: 4745084 (1988-05-01), Rowson et al.
patent: 5084404 (1992-01-01), Sharpe-Geisler

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