Method of making silicon-on-porous-silicon by ion implantation

Details Method of making silicon-on-porous-silicon by ion implantation Method of making silicon-on-porous-silicon by ion implantation

1993-05-11

1995-02-07

Breneman, R. Bruce

Fishing, trapping, and vermin destroying

437 18, 437 20, 437 57, 118DIG1, 118DIG3, H01L 21302

Patent

active

053875419

DESCRIPTION:

BRIEF SUMMARY
This invention relates to a method of producing silicon-on-porous-silicon material and to material and device production therefrom.
Porous silicon is a well known material (e.g. G Bomchil et al., Applied Surface Science 41/42 p604 1989). It can be obtained by anodic dissolution (anodizing) of silicon in hydrofluoric acid solutions. It is characterised by a network of fine popes, the number and size of which are determined by doping level of the silicon, dopant impurity type of the silicon and electrochemical parameters during anodizing. Subsequent oxidation of the porous silicon produces an insulating material.
Oxidized porous silicon provides one of the more promising materials for producing SOI (silicon-on-insulator) devices (e.g. N J Thomas et al., IEEE Device Letters 10(3) p129 1989; S S Tsao, IEEE Circuits and Devices Magazine P3 Nov.1987; K Imai and H Unno, IEEE Transactions on Electron Devices ED-31(3) p297 1984). There are two main methods of producing silicon-on-oxidised-porous-silicon. These ape selective formation of porous silicon in order to isolate discrete silicon islands and direct epitaxial deposition on a porous silicon layer, each followed by oxidation of the porous silicon.
The latter of the two above methods has the practical disadvantage of requiring low temperature, minimum time, epitaxial growth conditions, in order to prevent restructuring the underlying porous silicon layer. This method is difficult to control when used for layers of thickness less than 0.25 .mu.m, and also expensive. For minimal, or zero, added defects the porous silicon must have a porosity of less than 50%. These porosity levels are difficult to achieve in any type of starting silicon material except in n.sup.- n.sup.+ and p.sup.+. These types of starting material are not optimum for subsequent use in SOI device manufacture. Consequently, SOI material made by this technique uses non-optimum starting material and hence results in a higher than desirable defect density.
In general, the two most used techniques for the selective formation of porous silicon are the Full Isolation by Porous Silicon (FIPOS) p-n approach and the n
.sup.+
approach. FIPOS (K Imai, Solid State Electronics 24 p159 1981) uses implantation of protons to form temporary n-type silicon islands in p-type silicon wafers. Subsequently, the p-type silicon only is anodized such that porous silicon completely surrounds the temporary n-type silicon islands. Oxidation converts the temporary n-type silicon to p-type and the porous silicon to SiO.sub.2. This technique suffers from a number of inherent disadvantages including those of wafer warpage due to lattice expansion occurring when the p-type porous silicon is oxidised, and also the presence of a thickness non-uniformity located at the centre of the islands. The non-uniformities inter alia induce dislocations within the islands and thus reduce electrical conformity of the n-type silicon.
The above problems were largely overcome by the use of the n
.sup.+
technique, where a thin epitaxial layer of n.sup.- silicon is grown on either a n.sup.+ doped epitaxial layer of silicon or onto a buried n.sup.+ silicon diffusion layer. This method minimises wafer warpage, due to a creation of thinner porous silicon layers, increases the dimensions of silicon islands for which isolation is possible, due to confinement of the porous silicon transformation to lateral dimensions, and eliminates the non-uniformity. This method requires state-of-the-art epitaxial low pressure chemical vapour phase deposition (LPCPD) techniques. Where this technique is used to grow submicron n.sup.- layers, it is particularly difficult to control. Also measurement of layer thicknesses thinner than approximately 0.5 .mu.m poses a problem as available techniques (e.g. SIMS, cross-sectional TEM and spreading resistance measurement) are destructive. Another disadvantage of this technique is that the extent of lateral anodisation is restricted to 50 .mu.m.
It is the aim of this invention to provide an alternative method of producing

REFERENCES:
patent: 5023200 (1991-06-01), Blewer
patent: 5238858 (1993-08-01), Matsushita
Bomchil, "Porous Silicon: The Material and Its Applications in Silicon-on-Insulator Technologies," Applied Surface Science 41/42 (1989) pp. 604-613.
Patent Abstracts of Japan vol. 8, No. 272 (E-284) (1709) Dec. 1984.
Nuclear Instruments & Methods in Physics Research-B vol. 19/20, No. 1 Feb. 1987 pp. 307-311 Thornton et al "Amorphisation of Silicon . . . ".
J. of Applied Physics vol. 58, No. 2, Jul. 1985, pp. 683-687 Seidel et al "Rapid Thermal Annealing of Dopants Implanted into Preamorphized Silicon".

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