Method of making shadow RAM cell having a shallow trench EEPROM

Details Method of making shadow RAM cell having a shallow trench EEPROM Method of making shadow RAM cell having a shallow trench EEPROM

1992-09-21

1995-03-21

Fourson, George

Fishing, trapping, and vermin destroying

437203, 437228, H01L 21308

Patent

active

053995163

ABSTRACT:
A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.

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"A 4M Bit NVRAM Technology Using a Novel Stacked Capacitor On Selectively Self-Aligned Flotox Cell Structure" I.E.D.M. 90, 931-933 (1990).

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