Method of making semiconductor memory device and memory cells th

Details Method of making semiconductor memory device and memory cells th Method of making semiconductor memory device and memory cells th

1992-08-14

1993-12-21

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 60, 437919, H01L 2170

Patent

active

052721027

ABSTRACT:
Methods of making semiconductor memory cells and semiconductor memory devices capable of improving the degree of integration and simplifying the overall manufacturing processes. Within a substrate made of a semiconductor material or an insulating material, at least one trench is formed to provide a capacitor region. In the trench are formed a plate electrode, a capacitor dielectric layer and a storage node electrode which constitute a capacitor. The semiconductor substrate may be used as the plate electrode. In this case, the trench has only the capacitor dielectric layer and the storage node electrode. At the inlet of the trench filled with the constituting elements of the capacitor, a gate electrode and a semiconductor layer as an active layer are formed to extend vertically perpendicular to the trench inlet. A bit line contact is formed on the semiconductor layer. Over the bit line contact are formed a bit line contact and a bit line, in this order.

REFERENCES:
patent: 4649625 (1987-03-01), Lu
patent: 4988637 (1991-01-01), Dhong et al.
patent: 5013680 (1991-05-01), Lowrey et al.
A Surrounding Gate Transister (SGT) Cell for 64/256Mbit DRAMS by: K. Sunouchi, et al. 24-IEDM 89; pp. 23-26.
Double LDD Concave (DLC) Structure for Sub-Half Micron Mosfet by: K. Sunouchi, et al. IEDM 88-227; pp. 226-229.

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