Method of making semiconductor integrated circuits

Details Method of making semiconductor integrated circuits Method of making semiconductor integrated circuits

1978-10-25

1981-01-27

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

148175, 148187, 357 41, 357 42, 357 44, 357 91, H01L 2704, H01L 2908, H01L 21265

Patent

active

042473438

ABSTRACT:
The proposed method of making semiconductor integrated circuits comprises sequential formation on a p-substrate of a first layer of n-regions, an epitaxial p-layer, a second layer of n-regions with an oxide layer, a third layer of p- and n-regions formed by opening holes in the oxides layer and ionic implantation of appropriate dopants, as well as deep diffusion of the latter, conducted in an inert medium, the final step being interconnection metallization. A semiconductor integrated circuit thus produced comprises p-resistors based on a portion of the epitaxial p-layer, confined by n-regions, n-p-n transistors each having a collector isolating it from the other circuit components and based on n-regions of the first and second layers, a base formed by a portion of the epitaxial p-layer and confined by the collector region, and an emitter in the form of an n-region of the third layer, made in the base region. The circuit also comprises p-n-p transistors in a common-collector arrangement, n-resistors and lateral p-n-p transistors based on n-regions of the second layer and shaped as a prism the entire base whereof is contiguous to the substrate and the surface portion whereof contains at least one p-region of the third layer and/or at least one n-region of the third layer, the hole concentration in the p-regions of the third layer being at least five times higher than the electron concentration in the n-regions of the second layer.

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patent: 4075039 (1978-02-01), Sloan, Jr.
patent: 4087900 (1978-05-01), Yiannoulos

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