Method of making semiconductor device with multi-levels of polyc

Details Method of making semiconductor device with multi-levels of polyc Method of making semiconductor device with multi-levels of polyc

1983-09-01

1985-01-22

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29577C, 29578, 29591, 357 59, H01L 2190

Patent

active

044943016

ABSTRACT:
A method of making a semiconductor device having multi-levels of polycrystalline silicon conductors insulated from each other and from the silicon substrate on which the semiconductor device if formed. In this method, each of the silicon oxide layers insulating the conductors from each other and from the substrate surface are each individually formed by thermal oxidation so that each is tailored in thickness and electrical characteristics for the particular purpose that each serves.

REFERENCES:
patent: 4240196 (1980-12-01), Jacobs et al.
patent: 4270262 (1981-06-01), Hori et al.
patent: 4397077 (1983-08-01), Derbenwick et al.

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