Method of making self-aligned shallow trench isolation

Details Method of making self-aligned shallow trench isolation Method of making self-aligned shallow trench isolation

2002-03-29

2003-09-30

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

C438S975000

Reexamination Certificate

active

06627510

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to semiconductor processes, and more particularly to methods of isolating device structures.
Several methods of isolating adjacent device structures, for example transistors, on a semiconductor substrate have been used. One process that has been used since the 1970s is local oxidation of silicon, commonly referred to as LOCOS. LOCOS is a locally selective oxidation isolation process. One of the limitations of the LOCOS process is due to lateral oxidation under a nitride mask used to define the isolation region, resulting in a characteristic “bird's beak” shape. The bird's beak reduces the effective channel width of the device and causes threshold voltage non-uniformity within the transistors to be formed. The LOCOS process also has the limitations of defect generation, segregation of doping in the field region, as well as other limitations known to those of ordinary skill in the art. For example, defects can be generated around the perimeter of the device. The segregation of boron into field oxide causes a reduction of field threshold voltage and increased field leakage current. In the worst case, devices can become electrically connected through the field region.
Another method of isolation is direct shallow trench isolation, also known as direct STI. This is a simple shallow trench isolation process. Trenches are etched in a silicon substrate through either an oxide or a nitride mask. The resulting trench is then refilled with silicon dioxide and planarized using a chemical mechanical polishing (CMP) process. A disadvantage of this process is that corners of the trenches must be rounded to prevent the formation of a parasitic edge transistor, gate oxide breakdown at the edge of the active regions, or both. Consequently, this process also causes channel width reduction and threshold voltage non-uniformity.
A modified STI process has also been used. Gate oxide is grown and a first polysilicon layer is deposited after well formation. Silicon trenches are etched through the gate oxide and the first polysilicon layer. The trenches are then refilled with oxide followed by a second polysilicon layer. The first polysilicon and the second polysilicon layer are both used to form at least a portion of the polysilicon gate electrode. The main drawback of this process is post-polish thickness control of the first polysilicon layer, which causes difficulty with end point detection of the gate polysilicon etch.
The various STI processes provide a flat surface, which makes lithographic patterning easier. However, there are no inherent alignment marks, so additional photoresist mask steps must be used to etch an alignment key
SUMMARY OF THE INVENTION
Accordingly, a modified STI process is provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. An alignment key may be formed by selectively etching the oxide layer. A third polysilicon layer may then be deposited and patterned using photoresist to form a gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process.


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