Method of making self-aligned IGFET

Details Method of making self-aligned IGFET Method of making self-aligned IGFET

1982-07-02

1985-08-06

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29578, 148 15, H01L 21265

Patent

active

045326959

ABSTRACT:
The IGFET is formed on a GaAs wafer which is coated with a layer of Si.sub.3 N.sub.4 and a SiO.sub.2 layer. The SiO.sub.2 is etched away in transistor areas, and ion implanting provides channel doping. A gate of refractory metal such as Mo is deposited and delineated. The gate and the SiO.sub.2 act as masks for ion implantation of the source and drain. The refractory metal gate allows subsequent annealing at high temperatures to activate the ion implanted species.

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patent: 4319395 (1982-03-01), Lund et al.
patent: 4325073 (1982-04-01), Hughes et al.
patent: 4348746 (1982-09-01), Okabayashi et al.
patent: 4364167 (1982-12-01), Donley

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