Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal
Reexamination Certificate
1996-04-04
2001-10-23
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making device or circuit responsive to nonelectrical signal
C438S075000, C438S144000
Reexamination Certificate
active
06306676
ABSTRACT:
FIELD OF INVENTION
The invention relates generally to the field of image sensors, and in particular to image sensors with pinned photodiodes. More specifically, the invention relates to high energy implants used to create pinned photodiodes.
BACKGROUND OF THE INVENTION
The use of photodiodes as photodetector elements in interline CCD image sensors is well known and has been discussed in various prior art documents. The problem of image lag and how a pinned-photodiode structure, in principle, can eliminate this lag has been discussed by N. Teranishi et al., in “No Image Lag Photodiodes Structure in the Interline CCD Image Sensor”, in IEDM Tech. Dig., pages 324-327, December 1982. However, in practice there are various manufacturing and processing difficulties that lead to the creation of residual potential wells and barriers at the transfer gate edge that can actually preclude making these photodiodes lag free as discussed by B. C. Burkey et al., in “The Pinned Photodiode For An Interline-Transfer CCD Image Sensor”, in IEDM Tech. Dig., pages 28-31, December, 1984. These difficulties arise from a general lack of self alignment of the photodiode implants to the transfer gate edge.
High-energy photodiode implants, using an n-type cathode layer, are used to simplify the process by eliminating long (in time), high-temperature drives as discussed by J. O. Borland and R. Koelsch, in “MeV Implantation Technology: Next Generation-Manufacturing With Current-Generation Equipment”, Solid-State Technology, December 1993, and to improve sensitivity by creation of a larger collection volume. Although the associated larger ion range of these higher implant energies lead to better photodiodes, they present difficulties in terms of self alignment of the photodiode to the transfer gate edge, and in the elimination of residual potential wells and barriers required for lag-free operation.
It should be apparent from the foregoing discussion that there remains a need within the art for a product and a process for making self-aligned photodiodes using high-energy implants that results in improved performance and simplified manufacturing.
SUMMARY OF THE INVENTION
Therefore, it is the object of this invention to overcome the above mentioned difficulties. It is a further object of this invention to provide a product and process for making a self aligned, high energy implanted photodiode defined by the steps of: providing an imaging area on a semiconductor substrate having at least one gate dielectric layer on a major surface with at least one gate electrode layer on top of the dielectric layer on the major surface; providing a CCD formed within the imaging area having a plurality of cells arranged such that each cell within the CCD is adjacent to at least one photodetector area and each photodetector is coupled to the CCD through a transfer gate, the photodetector area being defined such that the gate electrode layer and the gate dielectric layer are allowed to exist over photodetector areas during formation of the CCDs, then patterning a masking layer to block high energy implants such that openings in the masking layer are formed over the photodetector areas; anisotropically etching down through the gate electrode layer over the photodetector areas while leaving the gate dielectric layer essentially intact; and creating a photodiode within the photodetector areas via a high energy implant such that the photodiode is self aligned with at least one edge of the transfer gate.
The basic components of a typical interline CCD image sensor pixel are a photodiode used for signal detection and collection, a CCD used for charge transport of the signal charge to the output of the device, a transfer gate used to transfer the photocharge collected in the photodiode to the CCD, and channel stops used to isolate and contain charge within the various regions of the pixel. Both linear and area-arrays can be made of the interline type.
Typically, layers of polysilicon are used to form the gate electrodes of the CCD and the photodiode-to-CCD transfer gate. In a typical CCD process, these polysilicon layers are removed from over the photodiode during the formation of the CCDs and transfer gates. The photodiodes are then formed using the polysilicon transfer gates as masking layers to self align the photodiode implants to the edges of the transfer gates. However, if the energies used to implant the photodiodes are very high, the range of the ions may be greater than the thickness of the polysilicon layer. Hence, they may go into the underlying substrate thereby causing undesirable, lag-inducing wells and/or barriers at the input edge of the transfer gate, i.e., the implants are no longer self aligned to the transfer gate.
The present invention leaves layers used in creating the CCD gate electrodes (e.g., polysilicon) over the photodiodes (either entirely or partially) during formation of the CCDs, and then later in the fabrication process to come back and define the photodiode by the steps of: depositing a first masking layer (such as photoresist) over the device surface thick enough to block the high-energy photodiode implants, defining this masking layer so that openings are formed over where the photodiode will be implanted, anisotropically etching down through the CCD gate electrode material remaining over the photodiode and stopping on gate electrode dielectric material (e.g., SiO
2
), and then implanting the photodiode with high-energy ions in a self-aligned manner to the edge of the first masking layer and transfer gate edge.
The above and other objects of the present invention will become more apparent when taken in conjunction with the following description and drawings wherein identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.
ADVANTAGEOUS EFFECT OF THE INVENTION
The primary advantage of this process is that it provides a method of ion implanting a photodiode self-aligned to its transfer gate using high implant energies to make an interlaced, or non interlaced, interline photodiode imager with all the associated performance improvements and manufacturing simplifications. The self aligned feature of the process provides improved manufacturability and reduced image lag. The use of high-energy implantation for the photodiodes reduces processing time and improves the sensitivity of the sensor. Also, the present invention does not require any additional masking steps in a conventional CCD process.
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N. Teranishi, et al., “No Image Lag Photodiodes Structure in the Interline CCD Image Sensor”, IEDM Tech. Dig., pp. 324-327, Dec. 1982.
B. C. Burkey, et al, “The Pinned Photodiode for an Interline-Transfer CCD Image Sensor”, IEDM Tech. Dig., pp. 28-31, Dec. 1984.
J. O. Borland and R. Koelsch, “MeV Implantation Technology: Next Generation-Manufacturing With Current-Generation Equipment”, Solid-State Technology, pp. 1 through 8, Dec. 1993.
Kosman Stephen L.
Lavine James P.
Losee David L.
Stevens Eric G.
Eastman Kodak Company
Trinh Michael
Watkins Peyton C.
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