Method of making self-aligned field-effect transistor

Details Method of making self-aligned field-effect transistor Method of making self-aligned field-effect transistor

1987-01-20

1990-09-11

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 44, 437 45, 437 39, 437912, 148DIG106, 148DIG105, H01L 21338

Patent

active

049563084

ABSTRACT:
A self-aligned gate (SAG) transistor or FET is described which transistor overcomes several disadvantages of the prior art for making SAG field-effect transistors. The disadvantages noted above result from the fact that current SAG FET's have a symmetrical structure, with n+ regions on either side of the gate electrode. This invention provides a means of masking off a region on the drain side of the gate electrode before performing an n+ implant, so that the n+ implanted region is asymmetrical on the two sides of the gate electrode. This has the desired beneficial effect of reducing the parasitic source resistance, without the deleterious effects on gate-drain breakdown voltage, gate-drain capacitance, and output resistance that invariably accompany a high doping level on the drain side of the gate. Using this technique, substantially increased performance can be obtained from a self-aligned FET.

REFERENCES:
patent: 4396437 (1983-08-01), Kwok et al.
patent: 4434013 (1984-02-01), Bol
patent: 4491860 (1985-01-01), Lim
patent: 4532695 (1985-08-01), Schmermeyer
patent: 4574298 (1986-03-01), Yamagishi et al.
patent: 4642259 (1987-02-01), Vetanen et al.
patent: 4645563 (1987-02-01), Terada
patent: 4674174 (1987-06-01), Kishita et al.

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