Method of making self-aligned double density polysilicon lines f

Details Method of making self-aligned double density polysilicon lines f Method of making self-aligned double density polysilicon lines f

1993-06-24

1994-05-10

Fourson, George

Fishing, trapping, and vermin destroying

437 52, 437191, 437924, H01L 21265, H01L 27115

Patent

active

053106938

ABSTRACT:
A method of forming a closely spaced self-aligned polysilicon pattern of conductive lines is achieved. The method involves forming semiconductor device structures in and on a semiconductor substrate. An insulating layer is formed over the device structures. An insulating layer structure is formed over the semiconductor device structures. A conductive polysilicon layer is formed over the insulating layer. A silicon oxide layer is formed over the polysilicon layer. The oxide layer is now patterned by lithography and etching. The patterning of the oxide layer leaves a first pattern of the oxide over a first designated plurality of polysilicon conductor lines and a second pattern between the oxide which exposes the polysilicon layer over a second designated plurality of polysilicon conductor lines plus the planned spacing between the first and second plurality of polysilicon conductor lines. A uniform thickness silicon nitride layer is deposited over the oxide layer and the exposed polysilicon layer wherein the thickness is the width of the planned spacing. The nitride layer is anisotropically etched to produce sidewall structures having the width of the planned spacing. The exposed polysilicon layer is oxidized to form a silicon oxide layer thereon. The sidewall structures are removed by etching. The exposed polysilicon layer is anisotropically etched to form the closely spaced polysilicon conductor lines. The oxide layers over the polysilicon conductor lines are removed as by etching.

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patent: 5002896 (1991-03-01), Naruke
patent: 5114872 (1992-05-01), Roselle et al.

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