Method of making self-aligned bit-lines

Details Method of making self-aligned bit-lines Method of making self-aligned bit-lines

2000-09-18

2002-07-23

Powell, William A. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S745000, C438S753000, C438S756000

Reexamination Certificate

active

06423641

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for making bit-lines on a semiconductor wafer, and more particularly, to a method for making self-aligned bit-lines.
2. Description of the Prior Art
Dynamic random access memory (DRAM) comprises an enormous amount of memory cells, each of which comprises a metal oxide semiconductor (MOS) and a capacitor. Each MOS and capacitor links with bit-lines through word lines to determine the location of each memory cell.
The design of a capacitor of a memory cell is based on two electric pole layers. The upper layer is a field plate and the lower layer is a storage node. The two layers are separated by a cell dielectric layer. When one electric pole layer is subjected to a voltage, an electric charge of the corresponding value is induced in the other electric pole layer. The data storing and retrieving functions are achieved in this way. The lower layer storage node, in the form of a node contact acting as a connecting line, connects electrically with the drain of a MOS transistor to store and retrieve data.
In order to raise the density of DRAM, when making lower layer storage nodes of the DRAM, landing pads are generally used in forming node contacts, which connect the MOS and capacitor with bit-lines. However, with advances in wafer production, the size of dynamic memory cells is being designed smaller and smaller. For this reason, the improvement and control of DRAM production processes has become an important subject in the field.
Please refer to
FIGS. 1
to FIGS.
4
.
FIGS. 1
to
4
show the fabrication processes of a lower layer storage node
28
of a capacitor according to the prior art. As shown in
FIG. 1
, a semiconductor wafer
10
comprises a substrate
12
, a landing pad
16
located on the substrate
12
, a first dielectric layer
14
deposited on the surfaces of the substrate
12
and the landing pad
16
, two bit-lines
18
located on the first dielectric layer
14
for data transmission, and a second dielectric layer
23
deposited over the surfaces of the two bit-lines
18
and the first dielectric layer
14
. The two bit-lines are covered by a metallic silicide layer
20
, which lowers the contact resistance of the surfaces of the bit-lines
18
.
As shown in
FIG. 2
, according to the prior art method for making a node contact hole
26
, a photoresist layer
24
on the surface of the second dielectric layer
23
is formed, and a lithographic process is used to pattern the location of the node contact hole
26
by forming a hole
25
in the photoresist layer
24
. Next, an etching process is performed, using the photoresist layer
24
as a hard mask, to vertically remove the second dielectric layer
23
and then the first dielectric layer
16
along the hole
25
down to the surface of the landing pad
16
. A node contact hole
26
is formed on the landing pad
16
between the two bit-lines
18
.
As shown in
FIG. 3
, after removing the photoresist layer
24
, a doped polysilicon layer (not shown) is deposited over the surface of the substrate
10
, filling the node contact hole
26
. An etching back process or a chemical mechanical polishing (CMP) process is then used to level the doped polysilicon layer in the node contact hole
26
with the second dielectric layer
23
to form a node contact
27
.
Finally, as shown in
FIG. 4
, an amorphous silicon layer is evenly deposited over the surface of the substrate
10
, and a photolithographic process and an etching process are used to form a lower layer storage node
28
on top of the node contact hole
26
. A hemi-spherical grain (HSG) process is performed to increase the surface area of the lower layer storage node
28
.
FIG. 5
shows a misalignment that can occur when making the lower layer storage node
28
of a capacitor according to the prior art. When etching the amorphous silicon layer to make the storage node
28
, if the pattern of the location is not accurately transferred during the photolithographic process, a misalignment occurs. This misalignment allows the doped polysilicon layer in the node contact hole
26
(the node contact
27
) to be etched off during the etching of the amorphous silicon layer. This results in a recess
29
, which causes an insufficient thickness of the ONO layer over the doped polysilicon layer
27
in the recess
29
during later processes when forming a cell dielectric layer of oxide-nitride-oxide (ONO) over the storage node
28
. This, in turn, results in a low-quality product. Additionally, since the node contact
27
is made after the two bit-lines
18
, the line width of the bit-lines
18
must be made very narrow to avoid misalignment during the formation of the node contact hole
26
. Unfortunately, the narrowing of the line width results in a high resistance in the bit-lines
18
, which affects the transmission speed, and which may even interrupt data transmission in the bit-lines
18
.
Moreover, as shown in
FIGS. 1
to
4
, the process for making the lower layer storage nodes
28
of the DRAM requires two photolithographic processes to define the location of the node contact hole
26
and the storage node
28
. For this reason, a landing pad has to be made before hand, which increases the DRAM manufacturing costs. Furthermore, with the size of the substrate decreasing, the precision of the photolithographic pattern transfer is lowered, and the subsequent yield rate is thus lowered.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method for making a self-aligned bit-line on a semiconductor wafer.
Another objective of the present invention is to prevent the problem of misalignment that occurs when making storage nodes on a semiconductor wafer.
In the preferred embodiment, the semiconductor wafer comprises a silicon substrate, a plurality of word lines located on the silicon substrate and a first dielectric layer located on the surface of the semiconductor wafer, which covers each word line. The manufacturing method of the present invention involves first forming a plurality of bit-line contacts, which are level with the surface of the first dielectric layer, in the first dielectric layer. Next, a second dielectric layer is formed on the surface of the semiconductor wafer and a plurality of node contacts are formed, which are level with the surface of the second dielectric layer, in the second and first dielectric layers. Thereafter, portions of the second dielectric layer are removed to make the top of each node contact higher than the surface of the second dielectric layer. A spacer is formed around the top of each node contact. The top of each node contact and spacer are used as a hard mask to form a plurality of word lines in the second and first dielectric layers. A plurality of bit-line contacts contact with the bottom portion of every bit-line. Finally, a storage node is formed on each node contact.
In the present invention, bit-lines are formed based on a difference in height, which is created through the etching process of conducting layers, and the conducting layer left in the lower region assumes the function of a landing pad, so the entire manufacturing process is simplified and costs are reduced.


REFERENCES:
patent: 6159833 (2000-12-01), Lee et al.
patent: 6235639 (2001-05-01), Sandhu et al.

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