Metal working – Method of mechanical manufacture – Assembling or joining
Patent
1982-12-29
1985-08-27
Roy, Upendra
Metal working
Method of mechanical manufacture
Assembling or joining
29576B, 148 15, 148187, 357 235, 357 2312, 357 236, 357 91, H01L 2126, H01L 21265
Patent
active
045369445
ABSTRACT:
The process sequence is disclosed which applies a polycrystalline silicon gate material, then applies a chemical vapor deposition oxide over all surfaces, forming an effective sidewall on each of the polycrystalline silicon gate structures. An ion implantation step is then carried out to implant source and drain regions whose proximate edges are not aligned with the edges of the polycrystalline silicon gate material itself, due to the masking effect of the sidewall portion of the chemical vapor deposition oxide layer. Thereafter, the chemical vapor deposition oxide sidewall material is selectively removed for those FET device locations where an active FET device is desired to be formed in the operation of personalizing the read only storage or PLA product. Those locations are then ion implanted for source and drain extensions which are then self-aligned with the respective edges of the respective polycrystalline silicon gate electrodes. The process enables a significantly reduced turnaround time for personalizing read only memory arrays which contain FET memory devices having a shorter channel length, higher breakdown voltage characteristic, an almost zero channel hot electron effect, and a lower gate-to-source/drain diffusion overlap capacitance than most other FET read only memory devices.
REFERENCES:
patent: 4235011 (1980-11-01), Butler et al.
patent: 4282646 (1981-08-01), Fortino et al.
patent: 4356623 (1982-11-01), Hunter
patent: 4366613 (1983-01-01), Ogura et al.
patent: 4380866 (1983-04-01), Countryman, Jr. et al.
patent: 4406049 (1983-09-01), Tam et al.
patent: 4467520 (1984-08-01), Shiotari
patent: 4472871 (1984-09-01), Green et al.
Ogura et al., IEEE-Trans. Electron Devices, vol. ED-27 (1980), 1359.
Ohta et al., IEEE-Trans. Electron Devices, ED-27 (1980), 1352.
Bracco Al M.
Edenfeld Arthur R.
Kotecha Harish N.
Abzug Jesse L.
Hoel John E.
International Business Machines - Corporation
Klitzman Maurice H.
Roy Upendra
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