Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Rendering selected devices operable or inoperable
Patent
1997-05-30
1999-08-31
Niebling, John F.
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Rendering selected devices operable or inoperable
438278, 438275, 257390, H01L 2182
Patent
active
059465581
ABSTRACT:
A method of making a read only memory device includes forming a gate oxide layer and a silicon nitride layer in sequence above a silicon substrate. The gate oxide layer and the silicon nitride layer are etched to define a plurality of parallel strips extending in a first direction. Ions are implanted, using the parallel strips as masks, into the silicon substrate to form a plurality of buried bit lines extending in the first direction. A sidewall spacer is formed on respective sidewalls of the parallel strips. A silicide layer is formed over an exposed surface of the respective bit lines. An insulating layer is formed to cover any exposed surfaces, and fill a space located between adjacent parallel strips and above the bit lines. A portion of the insulating layer is removed to expose the silicon nitride layer and form a planar surface. The silicon nitride layer is patterned to form a plurality of coding areas. A polysilicon layer is formed to cover the coding areas as well as any other exposed surfaces. The polysilicon layer is patterned to form a plurality of parallel word lines extending in a second direction perpendicular to the first direction. The word lines cover the coding areas and cross the bit lines. The area where each word line crosses with two adjacent bit lines forms a read only memory cell. A self-aligned coding operation is performed to define the read only memory cells as having an on or off state.
REFERENCES:
patent: 5084418 (1992-01-01), Esquivel et al.
patent: 5712203 (1998-01-01), Hsu
Murphy John
Niebling John F.
United Microelectronics Corp.
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