Method of making reliable wafer level chip scale package...

Details Method of making reliable wafer level chip scale package... Method of making reliable wafer level chip scale package...

2011-07-05

2011-07-05

Alanko, Anita K (Department: 1713)

Etching a substrate: processes

Forming or treating electrical conductor article

C216S017000, C216S018000, C216S052000, C427S096500, C029S832000, C438S106000

Reexamination Certificate

active

07972521

ABSTRACT:
The present invention relates to a method of making a robust wafer level chip scale package and, in particular, a method that prevents cracking of the passivation layer during solder flow and subsequent multiple thermal reflow steps. In one embodiment, a passivation layer that is formed using an insulating material applied in a highly compressive manner is used. In another aspect, another layer is applied over the passivation layer to assist with preventing cracking of the passivation layer.

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