Semiconductor device manufacturing: process – Chemical etching – Altering etchability of substrate region by compositional or...
Reexamination Certificate
2006-06-27
2006-06-27
Goudreau, George A. (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Altering etchability of substrate region by compositional or...
C438S455000, C438S458000, C438S514000, C438S690000
Reexamination Certificate
active
07067430
ABSTRACT:
A method of forming a silicon-germanium layer on an insulator includes depositing a layer of silicon-germanium on a silicon substrate to form a silicon/silicon-germanium portion; implanting hydrogen ions into the silicon substrate between about 500 Å to 1 μm below a silicon-germanium/silicon interface; bonding the silicon/silicon-germanium portion to an insulator substrate to form a couplet; thermally annealing the couplet in a first thermal annealing step to split the couplet; patterning and etching the silicon-germanium-on-insulator portion to remove portions of the silicon and SiGe layers; etching the silicon-germanium-on-insulator portion to remove the remaining silicon layer; thermally annealing the silicon-germanium-on-insulator portion in a second annealing step to relaxed the SiGe layer; and depositing a layer of strained silicon about the SiGe layer.
REFERENCES:
patent: 6767802 (2004-07-01), Maa et al.
patent: 6825086 (2004-11-01), Lee et al.
patent: 6852652 (2005-02-01), Maa et al.
patent: 6992025 (2006-01-01), Maa et al.
patent: 2002/0168802 (2002-11-01), Hsu et al.
K. Kim et al.,Strained Si for sub-100 nm MOSFETs, Proceedings of the 3rd International Conference on SiGe Epitaxy and Heterostructures, Sante Fe, New Mexico, Mar. 9-12, 2002, p. 125.
M. Bruel et al.,Smart-Cut: A New Silicon On Insulator Material Technology Based on Hydrogen Implantation and Wafer Bonding, Jpn. J. Appl. Phys., vol. 36, 1636 (1997).
Z.-Y. Cheng et al.,SiGe-on insulator(SGOI):Substrate Preparation and MOSFET Fabrication for Electron Mobility Evaluation, 2001 IEEE International SOI Conference Proceedings p. 13.
Z. Cheng et al.,Relaxed Ssilicon-Germanium on Insulator Substrate by Layer Transfer, Journal of Electronics Materials, vol. 30, No. 12, 2001, L37.
G. Taraschi et al.,Relaxed SiGe on Insulator Fabricated via Wafer Bonding and Layer Transfer: Etch-back and Smart-Cut Alternatives, Electrochemical Society Proceedings vol. 2001-3, p. 27.
L.-J. Huang et al.,Carrier Mobility Enhancement in Strained Si-on-Insulator Fabricated by Wafer Bonding, 2001 Symposium on VLSI Technology Digest of Technical Papers, p. 57.
7. T.A. Langdo et al.,Preparation of Novel SiGe-Free Strained Si on Insulator Substrates, 2002 IEEE International SOI Conference Proceedings, Oct. 2001, p. 211.
H. Yin et al.,Strain relaxation of SiGe islands on compliant oxide, Journal of Applied Physics, 91, 2002, 9718.
Hsu Sheng Teng
Lee Jong-Jan
Maa Jer-Shen
Tweet Douglas J.
Goudreau George A.
Sharp Laboratories of America Inc.
Varitz, P.C. Robert D.
LandOfFree
Method of making relaxed silicon-germanium on insulator via... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of making relaxed silicon-germanium on insulator via..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making relaxed silicon-germanium on insulator via... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3706851