Fishing – trapping – and vermin destroying
Patent
1993-06-17
1995-11-21
Thomas, Tom
Fishing, trapping, and vermin destroying
437 39, 437203, H01L 218258
Patent
active
054686610
ABSTRACT:
This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44. Other devices and methods are also disclosed.
REFERENCES:
patent: 4129879 (1978-12-01), Tantraporn et al.
patent: 4186410 (1980-01-01), Cho et al.
patent: 4632710 (1986-12-01), Van Rees
patent: 5045502 (1991-09-01), Lau et al.
patent: 5077231 (1991-12-01), Plumton et al.
patent: 5089431 (1992-02-01), Slatter et al.
patent: 5116455 (1992-05-01), Daly
Campbell, et al., "150 Volt Vertical Channel GaAs FET", IEEE-IEDM, 1982, pp. 258-260.
Campbell, et al., "Trapezoidal-Groove Schottky-Gate Vertical-Channel GaAs FET (GaAs Static Induction Transistor", IEEE Electron Device Letters, vol. EDL-6, No. 6, Jun. 1985, pp. 304-306.
Mori, et al., "A High Voltage GaAs Power Static Induction Transistor", Chemical Abstracts of the 19th Conference on Solid State Devices and Materials, Tokyo, 1987, pp. 279-282.
Frensley, et al., "Design and Fabrication of a GaAs Vertical MESFET", IEEE Transactions on Electron Devices, vol. ED-32, No. 5, May 1985, pp. 952-956.
Alferov, et al., "Buried-Gate Gallium Arsenide Vertical Field-Effect Transistor", Soviet Technical Physics Letters, vol. 12, No. 2, Feb. 1986, pp. 77-78.
Makimoto, et al., "AlGaAs/GaAs Heterojunction Bipolar Transistors with Heavily C-Doped Base Layers Grown by Flow-Rate Modulation Epitzxy", Applied Physics Letters, vol. 54, No. 1, 2 Jan. 1989, pp. 39-41.
"High-Speed Semiconductor Devices" edited by S. M. Sze, AT&T Bell Laboratories, & National Chiao Tung University; A Wiley-Interscience Publication, John Wiley & Sons, Inc. pub. 1990 pp. 262-265.
"Low Energy Ion Beam and Plasma Modification of Materials Symposium", Anaheim, Calif.; Apr. 30-May 2, 1991 Plasma etching of GaAs & InP (Abstract).
Kim Tae S.
Plumton Donald L.
Yang Jau-Yuann
Yuan Han-Tzong
Burton Dana L.
Donaldson Richard L.
Kesterson James C.
Texas Instruments Incorporated
Thomas Tom
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