Method of making power VFET device

Fishing – trapping – and vermin destroying

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437 39, 437203, H01L 218258

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054686610

ABSTRACT:
This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44. Other devices and methods are also disclosed.

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