Method of making plastic package for a surface mounted integrate

Details Method of making plastic package for a surface mounted integrate Method of making plastic package for a surface mounted integrate

1997-08-26

1999-11-02

Picardat, Kevin M.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

438106, 438121, 438124, H01L 2144, H01L 2148, H01L 2150

Patent

active

059769149

ABSTRACT:
In accordance with the invention, integrated circuit dies may be packaged in a plastic package employing an area area array technology such as a conductive ball grid array, column grid array or pin grid array. One aspect of the invention is an integrated circuit package (10) which includes an electronic circuit enclosed by a plastic body (12, 14). The molded plastic body has a first major surface opposing a second major surface. The first major surface of integrated circuit (10) has a plurality of openings therein. One of a plurality of conductive pads (18) is adjacent to each one of the openings and is electrically connected to the electronic circuit. Each of a plurality of conductors (20) is electrically connected to one of the pads (18) and protrudes from one of the openings (22).

REFERENCES:
patent: 5200367 (1993-04-01), Ko
patent: 5474957 (1995-12-01), Urushima
patent: 5736432 (1998-04-01), Mackessy
patent: 5753532 (1998-05-01), Sim

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