Method of making planarized Josephson junction devices

Details Method of making planarized Josephson junction devices Method of making planarized Josephson junction devices

1982-03-26

1983-11-29

Morgenstern, Norman

Coating processes

Electrical product produced

Superconductor

427 99, 427250, 4272554, 4272555, 4272557, 427404, 4274192, 156656, 1566591, H01L 3924

Patent

active

044180950

ABSTRACT:
The present invention teaches a method of planarizing built-up vacuum deposited surfaces or areas on Josephson junction and semiconductor devices so that successively deposited layers do not replicate the undulations of previous layers. After a surface layer is deposited in a vacuum system and part of the surface is etched, a raised surface is generated. A photoresist lift-off stencil is applied to the surface to be preserved and the material to be removed is removed by isotropically etching so as to leave an overhang or ledge of photoresist material over the area of the material retained. A new layer of material is now deposited by vacuum deposition so as to almost fill the area to be planarized. A small gap remains between the top of the new material being vacuum deposited and the botton of the photoresist stencil so that solvent can be introduced to the stencil. When the photoresist stencil is removed, the top of surface being preserved is substantially planar with the new layer of material.

REFERENCES:
patent: 3985597 (1976-10-01), Zielinski
patent: 4123565 (1978-10-01), Sumitomo et al.
patent: 4129167 (1978-12-01), Sigsbee
patent: 4224361 (1980-09-01), Romankiw
patent: 4256816 (1981-03-01), Dunkleberger
patent: 4339305 (1982-07-01), Jones
patent: 4353935 (1982-10-01), Symersky
Greiner et al., Fabrication Process for Josephson Integrated Circuits, IBM J. Res. Develop., vol. 24, No. 2, Nov. 1980.

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