Method of making planar III-V compound device by ion implantatio

Details Method of making planar III-V compound device by ion implantatio Method of making planar III-V compound device by ion implantatio

1983-02-07

1984-06-05

Roy, Upendra

Metal treatment

Compositions

Heat treating

29571, 29576B, 148187, 357 61, 357 91, H01L 21263, H01L 2126

Patent

active

044526466

ABSTRACT:
A planar process and new structure which leads to large scale integration capability by utilizing selective ion implantation into semi-insulating Gallium Arsenide substrates or any other compound semi-conducting material to yield isolated depletion enhancement mode JFETS and MESFETS, p-n junction and Schottky diodes, resistors and hot electron current limiters. The planar structure provides relatively simple integrated circuit fabrication which results in an increase of circuit device reliability and thereby improves not only the ease of fabrication but thereby increases yield of enhancement mode JFETS and MESFETS and other like devices in integrated circuit fabrication. In addition improved device structure is possible which increases device speed.

REFERENCES:
patent: 4038563 (1977-07-01), Zuleeg et al.
patent: 4108686 (1978-08-01), Jacobus, Jr.
patent: 4314858 (1982-02-01), Tomasetta et al.
patent: 4372032 (1983-02-01), Collins et al.

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