Method of making MOS FETs using silicate glass layer as gate edg

Details Method of making MOS FETs using silicate glass layer as gate edg Method of making MOS FETs using silicate glass layer as gate edg

1985-01-24

1986-08-05

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 148 15, 148187, 148DIG133, 148DIG82, 357 233, 357 91, H01L 2995, H01L 21283, H01L 21225

Patent

active

046034722

ABSTRACT:
A method for the manufacture of a large scale integration (LSI) MOS field effect transistor wherein a gate electrode is generated on a doped silicon substrate, source/drain regions are formed by ion implantation using the gate electrode as an implantation mask and the source/drain regions are shielded by means of an oxide layer extending to the sidewalls of the gate electrode so that the diffusion of the implanted source/drain regions under the gate electrode area are reduced. The specific improvement of the present invention involves applying a readily flowable silicate glass layer as a gate edge masking for the source/drain ion implantation after formation of the gate electrode, the silicate glass layer being applied by deposition from the vapor phase at a thickness such that the dopant ions in the subsequent source/drain ion implantation are still implanted into the zone near the surface under the silicate glass layer but ion implantation into the zones at the edges of the gate is suppressed.

REFERENCES:
patent: 440473 (1983-09-01), Sasaki
patent: 4345366 (1982-08-01), Brower
patent: 4348802 (1982-09-01), Shirato
patent: 4356623 (1982-11-01), Hunter
patent: 4366613 (1983-01-01), Ogura et al.
patent: 4499653 (1985-02-01), Kub et al.
patent: 4532697 (1985-08-01), Ko
patent: 4535528 (1985-08-01), Chen et al.
Tsang et al, "Fabrication of High-Performance LDDFET's with Oxide Sidewall-Spacer Technology", IEEE Transactions, vol. ed-29, No. 4, Apr. 1982.
Ogura et al, "Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor", IEEE Transactions, vol. ed-27, No. 8, Aug. 1980.
Kern et al, RCA Review, vol. 43, Sep. 1982.

Affiliated with

Also associated with

Rating

Method of making MOS FETs using silicate glass layer as gate edg does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making MOS FETs using silicate glass layer as gate edg, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making MOS FETs using silicate glass layer as gate edg will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-962645