Method of making memory cells with peripheral transistors

Details Method of making memory cells with peripheral transistors Method of making memory cells with peripheral transistors

1995-01-10

1996-07-23

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 52, H01L 218247

Patent

active

055389120

ABSTRACT:
In a semiconductor memory device according to the present invention, a conductive layer is formed on a field oxide film in a boundary region on the main surface of a semiconductor substrate. A floating gate electrode, an interlayer insulating film, and a control gate electrode are formed on the semiconductor substrate in a memory cell array region with a gate insulating film interposed therebetween. A gate electrode is formed in a peripheral circuit region with the gate insulating film interposed therebetween. An interlayer insulating film is formed on the conductive layer, the gate electrode, and the control gate electrode. A contact hole is formed at a predetermined position of the interlayer insulating film. An interconnection layer is selectively formed on the interlayer insulating film including the inner surface of the contact hole. According to the present invention, it is possible to prevent formation of a concave portion on the surface of the field oxide film in the boundary region. It is also possible to protect the memory cell array region from an external noise by forming the conductive layer on the field oxide film in the boundary region and by fixing the potential of the conductive layer.

REFERENCES:
patent: 4829361 (1989-05-01), Sagara et al.
patent: 4849366 (1989-07-01), Hsu et al.
patent: 4907058 (1990-03-01), Sakai
patent: 5175120 (1992-12-01), Lee
patent: 5183773 (1993-02-01), Miyata
patent: 5352620 (1994-10-01), Komori et al.

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