Method of making low leakage shallow junction IGFET devices

Details Method of making low leakage shallow junction IGFET devices Method of making low leakage shallow junction IGFET devices

1980-12-10

1982-05-18

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29577C, 148 15, 148187, H01L 2122, H01L 2126

Patent

active

043297730

ABSTRACT:
A method for forming shallow low leakage ion implanted source/drain regions in an integrated circuit environment including semirecessed oxide isolation regions in which high parasitic device threshold voltages are provided by an oxidizing/annealing post implant process. Arsenic ions are implanted into a recessed oxide isolated substrate followed by a wet oxidation process and a non-oxidizing annealing process for a period of time to provide a passivating dielectric over low leakage source/drain regions of less than one micron junction depth and to provide adequate high temperature annealing to reduce the charge effects in the oxide isolation regions caused by the implanted arsenic ions.

REFERENCES:
patent: 4118250 (1978-10-01), Horng et al.
patent: 4151010 (1979-04-01), Goth
patent: 4160987 (1979-07-01), Dennard et al.
patent: 4170492 (1979-10-01), Bartlett et al.
patent: 4170500 (1979-10-01), Crossley
patent: 4258077 (1981-03-01), Mori et al.
patent: 4282646 (1981-08-01), Fortino et al.
patent: 4294002 (1981-10-01), Jambotkar et al.
Dennard et al., "Design of Ion-Implanted Mosfet's . . . ," IEEE J. Solid-State Circuits, vol. SC-9, No. 5 (10/74), pp. 256-267.
Prussin et al., "Adaption of Ion Implantation . . . ," Extended Abstracts, Electro Chem. Soc., Spring Meeting, vol. 74-1, Abst. #85, May 12-17, 1974, pp. 213-215.
Bogardus et al., "Removal of Implant Damage," IBM Tech. Discl. Bull., vol. 18, No. 10, (3/76), p. 3301.
Tice, et al., "The Isochronal Annealing . . . of Silicon . . . , " Extended Abstracts, Electrochem. Soc. Fall Meeting, vol. 76-2 Abs. #334, Oct. 17-21, 1976, pp. 863-864.
Varma et al., "Abrupt Junctions by Ion-Implantation . . . ," Extended Abstracts, Electrochem. Soc. Spring Meeting, vol. 79-1, Abs. #112, May 6-11, 1979, pp. 310-313.
Wada et al., "Arsenic Ion-Implanted Shallow Junction, " J. Electrochem. Soc., vol. 127, No. 2 (1980) pp. 461-466.
Muller et al., "Influence of an Oxidizing Annealing Ambient . . . ," J. Electrochem. Soc., vol. 122, No. 9 (1975), pp. 1234-1238.
Hunter et al., "1.mu.m Mosfet VLSI Technology: Part V . . . ," IEEE Tr. Electron Devices, vol. ED-26, No. 4 (1979), pp. 353-359.
Geipel et al., "Low Leakage Implanted Source," IBM Tech. Discl. Bull., vol. 18, No. 2 (1975), p. 337.

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