Method of making low leakage N-channel SOS transistors utilizing

Details Method of making low leakage N-channel SOS transistors utilizing Method of making low leakage N-channel SOS transistors utilizing

1980-05-29

1983-07-19

Saba, W. G.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 29579, 148 15, 148175, 148187, 156649, 1566591, 357 4, 357 23TF, 357 52, 357 56, H01L 2186, H01L 2120

Patent

active

043935729

ABSTRACT:
A self-aligned method of implanting the edges of NMOS/SOS transistors is described. The method entails covering the silicon islands with a thick oxide layer, applying a protective photoresist layer over the thick oxide layer, and exposing the photoresist layer from the underside of the sapphire substrate thereby using the island as an exposure mask. Only the photoresist on the islands' edges will be exposed. The exposed photoresist is then removed and the thick oxide is removed from the islands edges which are then implanted.

REFERENCES:
patent: 3740280 (1973-06-01), Ronen
patent: 3890632 (1975-06-01), Ham et al.
patent: 4070211 (1978-01-01), Harari
patent: 4174217 (1979-11-01), Flatley
patent: 4178191 (1979-12-01), Flatley
patent: 4242156 (1980-12-01), Peel
patent: 4277884 (1981-07-01), Hsu

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