Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2002-07-25
2003-09-23
Talbott, David L. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S110000, C438S113000, C438S124000
Reexamination Certificate
active
06624007
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of making a leadframe used for fabricating a semiconductor device. It also relates to a method of making a semiconductor device by using such a leadframe.
2. Description of the Related Art
FIG. 19A
of the accompanying drawings shows a conventional surface-mounting semiconductor device. As illustrated, the device, generally indicated by reference numeral
9
, includes a first conductor
90
, a second conductor
91
and a semiconductor chip
92
. The first conductor
90
has a lower surface (terminal surface)
90
a
and an upper surface (bonding surface)
90
b
. Likewise, the second conductor
91
has a lower surface (terminal surface)
91
a
and an upper surface (bonding surface)
91
b
. The first conductor
90
generally consists of two portions, i.e., a thinner portion
90
c
and the remaining thicker portion, which corresponds in position to the terminal surface
90
a.
The semiconductor chip
92
is formed with a lower and an upper electrodes (not shown) on its bottom and head surfaces, respectively. The chip
92
is mounted on the first conductor
90
, with its lower electrode electrically connected to the bonding surface
90
b
. The upper electrode of the chip
92
is connected to the bonding surface
91
b
of the second conductor
91
via a connection wire
93
. The chip
92
and the wire
93
are entirely covered by a resin package
94
. On the other hand, the terminal surfaces
90
a
,
91
a
of the first and the second conductor
90
,
91
are exposed in the bottom surface
94
a
of the package
94
.
The semiconductor device
9
is fabricated in the following manner. First, a suitable electroconductive frame (leadframe) is prepared. This frame includes portions to be used as the first and the second conductors
90
,
91
. The semiconductor chip
92
is mounted on the frame, and then the bonding of the wire
93
is performed. The mounted chip
92
and the wire
93
are enclosed by a resin material. Finally, the thus obtained intermediate product is diced into smaller pieces, one of which provides the semiconductor device
9
shown in FIG.
19
A.
As noted above, the first conductor
90
of the device
9
is formed with a thinner portion
90
c
. This nonuniform thickness results from the corresponding configuration of the leadframe used for making the device
9
. Conventionally, such a leadframe is produced from an electroconductive strip by etching. Specifically, referring to
FIG. 20A
, a mask
96
is formed by e.g. photolithography on the upper and lower surfaces of an electroconductive plate
95
of an uniform thickness. The mask
96
is formed with openings
97
A and
97
B corresponding in position to the prescribed regions to be etched. Upon application of an etchant, as shown in FIG.
20
B, the prescribed portions of the plate
95
are etched away from above and/or below by half the thickness of the plate
95
. As a result, some through-holes
99
are formed in the plate
95
at the places where the upper and the lower openings
97
A,
97
B overlap, whereas some “half-depth dents” are formed at the places where only the lower openings
97
B are provided. Due to the provision of the half-depth dents, the plate
95
is formed with thin-walled portions
98
whose thickness is generally half the original thickness of the plate
95
.
The conventional leadframe fabrication method has the following drawbacks.
The first problem is that the above etching process is rather difficult to perform on a hoop material. Thus, before a mask-forming process and etching process are carried out, the hoop needs to be cut into shorter pieces so that proper etching result can be obtained. Apparently, this additional cutting procedure diminishes the production efficiency.
The second problem is that the mask-forming process is time-consuming. Also, after the etching process is over, the mask
96
formed on the plate
95
needs to be removed. This results in a decrease in efficiency and an increase in cost.
The third problem is that the required configuration of the parts of the leadframe often fails to be obtained by etching. Referring to
FIG. 19B
, which is a plan view showing the first conductor
90
and the semiconductor chip
92
mounted on the conductor
90
, the first conductor
90
is provided with round corners resulting from inevitable spreading of the etchant, even when use is made of an etching mask formed with a completely rectangular opening in it. Unfavorably, the round-cornered first conductor
90
has a smaller effective bonding area for the chip
90
than otherwise. This means that the marginal portion
90
d
of the conductor
90
is not used for any productive purposes but merely cause an increase in overall size of the semiconductor device
9
.
SUMMARY OF THE INVENTION
The present invention has been proposed under the circumstances described above. It is, therefore, an object of the present invention to provide a fabrication technique, whereby a compact semiconductor device can be produced efficiently and at low cost.
According to a first aspect of the present invention, there is provided a method of making a semiconductor device. The method comprises the steps of: mounting a semiconductor chip on a leadframe; producing an intermediate product by forming a packaging layer to enclose the chip, wherein the intermediate product includes the leadframe, the chip and the packaging layer; and cutting the intermediate product. The cutting step is performed by using a first cutter of a first thickness and a second cutter of a second thickness greater than the first thickness. The first cutter is used for making a “full cut” in the leadframe, while the second cutter is used for making a “partial cut” in the leadframe. In this specification, the “full cut” implies that the leadframe is cut through in its thickness direction. The “partial cut”, on the other hand, implies that the leadframe is not cut through in its thickness direction (nor in any other directions) and the depth of the cut is smaller than the thickness of the leadframe. The determination of where the full cut and the partial cut are to be made is based on a common cut line, so that the full cut and the partial cut coact to prevent the formation of burrs at the cut site.
The partial cut may be made after or before the full cut is made.
Preferably, the method of the present invention may further comprise the step of preparing the leadframe by processing an electroconductive material of a uniform thickness. In this case, the leadframe-preparing step may include sub-steps such as first punching, stamping and second punching. The first punching may be performed for forming a patterned region in the electroconductive material, the stamping may be performed for compressing the patterned region to provide a stamped portion of a thickness smaller than the uniform thickness of the electroconductive material, and the second punching may be performed for removing an unnecessary part from the stamped portion.
Preferably, the first punching may produce a “land” and an opening adjacent to the land. In this arrangement, when the subsequent stamping compresses the land, this land is allowed to spread out into the opening. This is advantageous to preventing unfavorable stress due to the stamping from remaining in the leadframe.
Preferably, the packaging layer may be formed in a manner such that it covers the stamped portion entirely but allows part of the leadframe to be exposed.
According to a second aspect of the present invention, there is provided a method of making a leadframe for fabricating a semiconductor device. The method may comprise the steps of: performing first punching on an electroconductive material of a uniform thickness; stamping the electoroconductive material to form a stamped portion of a thickness smaller than the uniform thickness of the electoroconductive material; and performing second punching on the electroconductive material to remove an unnecessary part from the stamped portion.
Other features and advantages
Kobayakawa Masahiko
Maeda Masahide
Merchant & Gould P.C.
Rohm & Co., Ltd.
Talbott David L.
Thai Luan
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