Method of making layout design to eliminate process antenna effe

Details Method of making layout design to eliminate process antenna effe Method of making layout design to eliminate process antenna effe

1995-02-13

1996-05-07

Fourson, George

Fishing, trapping, and vermin destroying

437228, 437225, 156643, H01L 21283, H01L 213065

Patent

active

055146236

ABSTRACT:
A multi-level conductive interconnection for an integrated circuit is formed in a silicon substrate, wherein there are large contact pad areas at the periphery of the interconnection. A patterned layer of a polysilicon layer is formed on the substrate to act as a first contact to the integrated circuit. An insulating layer is formed over the polysilicon layer, and openings to the polysilicon layer are formed through the insulating layer. A first layer of metal is formed on the insulator such that the metal electrically connects to the polysilicon through the openings, and also forms large contact pad areas. The first metal is patterned to form an electrical break between the large contact pad areas and the integrated circuit. This break prevents electrical damage to the integrated circuit due to charge build-up during subsequent processing in a plasma environment. A second insulating layer is formed and patterned to provide openings for vias to the first metal layer. A second layer of metal is formed over the large contact pad area and over the electrical break such that the second metal electrically connects to the first metal, by direct contact to the first metal at the large contact pad area, and through the openings in the second insulator to the first metal interconnection. Finally, a passivation layer is formed over the second metal layer.

REFERENCES:
patent: 5342808 (1994-08-01), Brigham et al.
patent: 5393701 (1995-02-01), Ko et al.
"Gate Oxide Charging And Its Elimination for Metal Antenna Capacitor and Transistor in VLSI CMOS Double Layer Metal Technology", pub in Symposium on VLSI Technology, pp. 73-74 in Jun., 1988.

Affiliated with

Also associated with

Rating

Method of making layout design to eliminate process antenna effe does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making layout design to eliminate process antenna effe, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making layout design to eliminate process antenna effe will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1227039