Method of making large-scale EPROM memory with a checker board p

Details Method of making large-scale EPROM memory with a checker board p Method of making large-scale EPROM memory with a checker board p

1989-08-11

1991-09-10

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 43, 437 48, 437 49, 437 51, 437195, 437228, 437233, 357 235, H01L 2170

Patent

active

050473620

ABSTRACT:
An electrically programmable non-volatile memory comprises word lines (LM2) extending along rows, and bit lines (LB1) extending along columns. Each memory point (PM1) is constituted by a pair of MOS transistors (T22, T23) having a floating gate (23). A conductive area (25) is connected to the floating gates (23) of the two transistors (T22, T23) of each pair and is in register with the word line (LM2) connected to the memory point (PM1) made by the transistor pair. This word line (LM2) corresponds, at the position of this pair, to the control gate (28).

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patent: 4851365 (1989-07-01), Jeuch
patent: 4887238 (1989-12-01), Bengemont

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