Method of making isolated vertical PNP transistor in a complemen

Fishing – trapping – and vermin destroying

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437 52, 437 57, 437 29, H01L 21331, H01L 21336

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052486249

ABSTRACT:
A method and apparatus for an improved isolated vertical PNP in a complementary BICMOS process with EEPROM memory is provided. The isolated vertical PNP transistor is formed on a P-substrate with a P-epitaxial (EPI) layer. The collector of the vertical PNP transistor is isolated with an N- buried layer formed in the P substrate and an N+ buried layer on the sidewalls for isolation. The collector is formed with a P+ layer buried in the N- layer. Subsequently, the P- EPI layer is deposited and an N+ sinker is diffused down to the N+ buried layer to complete the isolation. The emitter of the vertical PNP transistor is formed during the same step as the P+ source/drain implant for the CMOS transistors. By forming the collector and its isolation regions in the substrate before depositing the EPI layer, the process is compatible with forming EEPROM which is done after the epi is deposited. An earlier implantation of the N base layer in the front-end of the process allows a deeper base junction depth, for formation of a high voltage PNP transistor. Alternately, the base can be formed later in the process, for a low voltage transistor. The presence of both high and low voltage transistors makes integration of EEPROM on the same chip practical. Only two dopant species (arsenic and boron) are used for the formation of N+, N- and P+ buried layers. Thus the present invention provides better manufacturability than the prior art processes which use three dopant species.

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